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a mixed signal dsp controller information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringeme nts of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. rev. 0 adsp-21990 key features adsp-219x, 16-bit, fixed point dsp core with up to 160 mips sustained performance 8k words of on-chip ram, configured as 4k words on- chip 24-bit program ram and 4k words on-chip 16-bit data ram external memory interface dedicated memory dma controller for data/instruction transfer between internal/external memory programmable pll and flexible clock generation circuitry enables full speed operation from low speed input clocks ieee jtag standard 1149.1 test access port supports on-chip emulation and system debugging 8-channel, 14-bit analog-t o-digital converter system, with up to 20 msps sampling rate (at 160 mhz core clock rate) three phase 16-bit center ba sed pwm generation unit with 12.5 ns resolution at 160 mhz core clock (cclk) rate dedicated 32-bit encoder interface unit with companion encoder event timer dual 16-bit auxiliary pwm outputs 16 general-purpose flag i/o pins three programmable 32- bit interval timers spi communications port with master or slave operation synchronous serial communications port (sport) capable of software uart emulation integrated watchdog timer dedicated peripheral interrupt controller with software priority control multiple boot modes precision 1.0 v voltage reference functional block diagram adc control vref pipeline flash adc clock generator/pll pm address/data dm address/data i/o bus 4k 16 dm ram 4k 24 pm ram external memory interface (emi) timer 0 timer 1 timer 2 4k 24 pm rom adsp-219x dsp core jtag test and emulation address data control i/o registers pwm generation unit encoder interface unit (and eet) auxiliary pwm unit flag i/o spi sport watchdog timer interrupt controller (icntl) por memory dma controller one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel:781/329-4700 www.analog.com fax:781/326-8703 ? 2003 analog devices, inc. all rights reserved.
adsp-21990 ?2? rev. 0 key features (continued) integrated power-on-reset (por) generator flexible power management with selectable power- down and idle modes 2.5 v internal operat ion with 3.3 v i/o operating temperature range of ?40oc to +85oc 196-ball mini-bga package 176-lead lqfp package target applications industrial motor drives uninterruptible power supplies optical networking control data acquisition systems test and measurement systems portable instrumentation table of contents general description . . . . . . . . . . . . . . . . . . . . 2 dsp core architecture . . . . . . . . . . . . . . . . . . . . . . . 3 memory architecture . . . . . . . . . . . . . . . . . . . . . . . . 4 internal (on-chip) memory . . . . . . . . . . . . . . . . . . 5 external (off-chip) memory . . . . . . . . . . . . . . . . . 5 external memory space . . . . . . . . . . . . . . . . . . . . . 5 i/o memory space . . . . . . . . . . . . . . . . . . . . . . . . . 5 boot memory space . . . . . . . . . . . . . . . . . . . . . . . . 6 bus request and bus grant . . . . . . . . . . . . . . . . . . . . 6 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 dsp peripherals architecture . . . . . . . . . . . . . . . . . . 6 serial peripheral interface (spi) port . . . . . . . . . . . . . 7 dsp serial port (sport) . . . . . . . . . . . . . . . . . . . . . 7 analog-to-digital conversion syst em . . . . . . . . . . . . 8 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pwm generation unit . . . . . . . . . . . . . . . . . . . . . . . 8 auxiliary pwm generation unit . . . . . . . . . . . . . . . . 9 encoder interface unit . . . . . . . . . . . . . . . . . . . . . . . 9 flag i/o (fio) peripheral unit . . . . . . . . . . . . . . . . 10 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 general-purpose timers . . . . . . . . . . . . . . . . . . . . . 10 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 peripheral interrupt controller . . . . . . . . . . . . . . . . 11 low power operation . . . . . . . . . . . . . . . . . . . . . . . 11 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 power-down core mode . . . . . . . . . . . . . . . . . . . 11 power-down core/peripherals mode . . . . . . . . . . 11 power-down all mode . . . . . . . . . . . . . . . . . . . . 12 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 reset and power-on reset (por) . . . . . . . . . . . . . . 12 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 booting modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 instruction set descript ion . . . . . . . . . . . . . . . . . . . 13 development tools . . . . . . . . . . . . . . . . . . . . . . . . . 13 designing an emulator-compatible dsp board . . . 14 additional information . . . . . . . . . . . . . . . . . . . . . . 14 pin function descriptions . . . . . . . . . . . . . 14 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 17 absolute maximum ratings . . . . . . . . . . 22 esd sensitivity . . . . . . . . . . . . . . . . . . . . . . . . 22 timing specifications . . . . . . . . . . . . . . . . 22 clock in and clock out cycle timing . . . . . . . . . 23 programmable flags cycle timing . . . . . . . . . . . 24 timer pwm_out cycle timing . . . . . . . . . . . . 24 external port write cycle timing . . . . . . . . . . . . 25 external port read cycle timing . . . . . . . . . . . . 26 external port bus request/grant cycle timing . . 27 serial port timing . . . . . . . . . . . . . . . . . . . . . . . . 28 serial peripheral interface port?master timing . 31 serial peripheral interface port?slave timing . . 32 jtag test and emulation port timing . . . . . . . 33 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 34 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 output disable time . . . . . . . . . . . . . . . . . . . . . . 34 output enable time . . . . . . . . . . . . . . . . . . . . . . 35 example system hold time ca lculation . . . . . . . 35 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . 35 outline dimensions . . . . . . . . . . . . . . . . . . . . 40 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . 41 general description the adsp-21990 is a mixed signal dsp controller based on the adsp-219x dsp core, suitable for a variety of high performance industrial motor control and signal processing applications that require the combination of a high performance dsp and the mixed signal integration of embedded control peripherals such as analog-to-digital conversion. the adsp-21990 integrates the fixed point adsp-219x family base architecture with a serial port, an spi compatible port, a dma controller, three programmable timers, general-purpose programmable flag pins, extensiv e interrupt capabilities, on- chip program and data memory spaces, and a complete set of embedded control peripherals that permits fast motor control and signal processing in a highly integrated environment. the adsp-21990 architecture is co de compatible with previous adsp-217x based admcxxx prod ucts. although the architec- tures are compatible, the adsp-21990, with adsp-219x architecture, has a number of en hancements over earlier archi- tectures. the enhancements to computational units, data address generators, and program sequencer make the adsp-21990 more flexible and easier to program than the previous adsp-21xx embedded dsps. indirect addressing options provide addressing flexibility? premodify with no update, pre- and post-modify by an immediate 8-bit, twos complement value and base address registers for easier implementation of circular buffering. the adsp-21990 integrates 8k words of on-chip memory con- figured as 4k words (24-bit) of program ram, and 4k words (16-bit) of data ram. fabricated in a high speed, low power, cmos process, the adsp-21990 operates with a 6.25 ns instruction cycle time for a 160 mhz cclk and with a 6.67 ns instruction cycle time for a 150 mhz cclk.
?3? rev. 0 adsp-21990 the flexible architecture and comprehensive instruction set of the adsp-21990 support multiple operations in parallel. for example, in one processor cycle, the adsp-21990 can: ? generate an address for th e next instruction fetch. ? fetch the next instruction. ? perform one or two data moves. ? update one or two data address pointers. ? perform a computational operation. these operations take place while the processor continues to: ? receive and transmit data through the serial port. ? receive or transmit data over the spi port. ? access external memory through the external memory interface. ? decrement the timers. ? operate the embedded contro l peripherals (adc, pwm, eiu, etc.). dsp core architecture ? 6.25 ns instruction cycle ti me (internal), for up to 160 mips sustained performance (6.67 ns instruction cycle time for 150 mips sustained performance). ? adsp-218x family code compat ible with the same easy to use algebraic syntax. ? single cycle inst ruction execution. ? up to 1m words of addres sable memory space with twenty four bits of addressing width. ? dual purpose program memory for both instruction and data storage. ? fully transparent instruction cache allows dual operand fetches in every instruction cycle. ? unified memory space permit s flexible address genera- tion, using two independent dag units. ? independent alu, multiplier/accumulator, and barrel shifter computational units with dual 40-bit accumulators. ? single cycle context switch between two sets of computa- tional and dag registers. ? parallel execution of co mputation and memory instructions. ? pipelined architecture supports efficient code execution at speeds up to 160 mips. ? register file computations with all nonconditional, non- parallel computational instructions. ? powerful program sequencer provides zero overhead looping and conditional instruction execution. ? architectural enhancements for compiled c code efficiency. ? architecture enhancements beyond adsp-218x family are supported with instruction set extensions for added registers, ports, and peripherals. the clock generator module of the adsp-21990 includes clock control logic that allows the user to select and change the main clock frequency. the module generates two output clocks: the dsp core clock, cclk; and the peripheral clock, hclk. cclk can sustain clock values of up to 160 mhz, while hclk can be equal to cclk or cclk/2 for values up to a maximum 80 mhz peripheral clock at the 160 mhz cclk rate. the adsp-21990 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. every single word instruction can be executed in a single processor cycle. the ad sp-21990 assembly language uses an algebraic syntax for ease of coding and readability. a compre- hensive set of development tools supports program development. the block diagram figure 1 shows the architecture of the embedded adsp-219x core. it contains three independent com- putational units: the alu, the multiplier/accumulator (mac), and the shifter. the computational units process 16-bit data from the register file and have provis ions to support multiprecision computations. the alu performs a standard set of arithmetic and logic operations; division pr imitives are also supported. the mac performs single cycle multiply, multiply/add, and multi- ply/subtract operations. the mac has two 40-bit accumulators, which help with overflow. the shifter performs logical and arith- metic shifts, normalization, denormalization, and derive exponent operations. the shifte r can be used to efficiently implement numeric format control, including multiword and block floating point representations. register usage rules influence placement of input and results within the computational units. for most operations, the com- putational unit data registers act as a data register file, permitting any input or result register to provide input to any unit for a computation. for feedback operations, the computational units let the output (result) of any unit be input to any unit on the next cycle. for conditional or multifunction instructions, there are restrictions on which data registers may provide inputs or receive results from each computational unit. for more information, see the adsp-219x dsp instruction set reference . a powerful program sequencer controls the flow of instruction execution. the sequencer supports conditional jumps, subrou- tine calls, and low interrupt overhead. with internal loop counters and loop stacks, the adsp-21990 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag ma intains and updates four 16- bit address pointers. whenever the pointer is used to access data (indirect addressing), it is pre- or post-modified by the value of one of four possible modify registers. a length value and base address may be associated with each pointer to implement automatic modulo addressing for circular buffers. page registers in the dags allow circular addressing within 64k word bound- aries of each of the 256 memory pages, but these buffers may not cross page boundaries. secondary registers duplicate all the primary registers in the dags; switching between primary and secondary registers provides a fast context switch.
adsp-21990 ?4? rev. 0 efficient data transfer in the co re is achieved with the use of internal buses: ? program memory address (pma) bus ? program memory data (pmd) bus ? data memory address (dma) bus ? data memory data (dmd) bus ? direct memory a ccess address bus ? direct memory access data bus the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (pmd and dmd) share a single external data bus. boot memory space and i/o memory space also share the external buses. program memory can store both instructions and data, permit- ting the adsp-21990 to fetch two operands in a single cycle, one from program memory and one from data memory. the dual memory buses also let the embedded adsp-219x core fetch an operand from data memory and the next instruction from program memory in a single cycle. memory architecture the adsp-21990 provides 8k words of on-chip sram memory. this memory is divided into two blocks: a 4k 24-bit (block 0) and a 4k 16-bit (block 1). in addition, the adsp-21990 provides a 4k 24-bit block of program memory boot rom (that is reser ved by ad i for boot load routines). the memory map of the adsp-21990 is illustrated in figure 2. as shown in figure 2, the two internal memory ram blocks reside in memor y page 0. the entire dsp memor y map consists of 256 pages (pages 0 to 255), a nd each page is 64k words long. external memory space consis ts of four memory banks (banks3?0) and supports a wide variety of memory devices. each bank is selectable using unique memory select lines ( ms3C0 ) and has configurable page boundaries, wait states, and wait state modes. the 4k words of on-chip boot rom populates the top of page 255, while the remain ing 254 pages are addressable off- chip. i/o memory pages differ from exter nal m emor y in that they are 1k word long, and the external i/o pages have their own select pin ( ioms ). pages 31?0 of i/o memory space reside on-chip and contain the configuration registers for the peripherals. both the adsp-219x core and dma capabl e peripherals can access the the entire memory map of the dsp. figure 1. block diagram data address b l o c k 2 system interrupt controller i/o data i/o registers (memory-mapped) control status buffers i/o processor cache 64 24-bit jtag test and emulation 6 addr bus mux data bus mux 16 20 pm address bus dm address bus pm data bus dm data bus px 24 16 adsp-219x dsp core program sequencer data register file mult barrel shifter alu dma controller input registers result registers 16 16-bit dag1 4 4 16 dag2 4 4 16 internal memory 24 24 address b l o c k 1 data data address b l o c k 0 24 bit 16 bit 16 bit four independent blocks programmable flags (16) timers (3) 3 dma connect dma address external port 18 i/o address 24 16 24 dma data embedded control peripherals and communications ports
?5? rev. 0 adsp-21990 note: the physical external memory addresses are limited by 20 address lines, and are determin ed by the external data width and packing of the external memo ry space. the strobe signals ( ms3-0 ) can be programmed to allow th e user to change starting page addresses at run time. internal (on-chip) memory the adsp-21990 unified program and data memory space consists of 16m locations that are accessible through two 24-bit address buses, the pma and dma buses. the dsp uses slightly different mechanisms to generate a 24-bit address for each bus. the dsp has three functions that support access to the full memory map. ? the dags generate 24-bit addresses for data fetches from the entire dsp memory address range. because dag index (address) registers are 16 bits wide and hold the lower 16 bits of the address, each of the dags has its own 8-bit page register (dmpgx) to hold the most significant eight address bits. before a dag generates an address, the program must set the dag dmpgx register to the appropriate memory page. the dmpg1 register is also used as a page register when accessing external memory. the program must set dm pg1 accordingly, when accessing data variables in external memory. a ?c? program macro is provided for setting this register. ? the program sequencer generates the addresses for instruction fetches. for relative addressing instructions, the program sequencer bases addresses for relative jumps, calls, and loops on the 24-bit program counter (pc). in direct addressing in structions (two word instructions), the instruction provides an immediate 24-bit address value. the pc allows linear a ddressing of the full 24-bit address range. ? for indirect jumps and ca lls that use a 16-bit dag address register for part of the branch address, the program sequencer relies on an 8-bit indirect jump page (ijpg) register to supply the most significant eight address bits. before a cross page jump or call, the program must set the program sequencer ijpg register to the appropriate memory page. the adsp-21990 has 4k word of on-chip rom that holds boot routines. the dsp starts executing instructions from the on-chip boot rom, which starts the boot process. see booting modes on page 13. the on-chip boot rom is located on page 255 in the dsp memory space map, st arting at address 0xff0000. external (off-chip) memory each of the adsp-21990 off-chip memory spaces has a separate control register, so applicatio ns can configure unique access parameters for each space. the access parameters include read and write wait counts, wait state completion mode, i/o clock divide ratio, write hold time extension, strobe polarity, and data bus width. the core clock and peripheral clock ratios influence the external memory access strobe widths. see clock signals on page 12. the off-chip memory spaces are: ? external memory space ( ms3C0 pins) ? i/o memory space ( ioms pin) ? boot memory space ( bms pin) all of the above off-chip memo ry spaces are accessible through the external port, which can be configured for 8-bit or 16-bit data widths. external memory space external memory space consists of four memory banks. these banks can contain a configurable number of 64 k word pages. at reset, the page boundaries for external memory have bank0 con- taining pages 1 to 63, bank1 containing pages 64 to 127, bank2 containing pages 128 to 191, an d bank3 containing pages 192 to 254. the ms3-0 memory bank pins select banks 3-0, respec- tively. both the adsp-219x core and dma capable peripherals can access the dsp external memory space. all accesses to external memory are managed by the external memory interface unit (emi). i/o memory space the adsp-21990 supports an additional external memory called i/o memory space. the io space consists of 256 pages, each containing 1024 addresses. this space is designed to support simple connections to peripherals (such as data convert- ers and external registers) or to bus interface asic data registers. the first 32k addresses (io pages 0 to 31) are reserved for on-chip peripherals. the upper 224k addresses (io pages 32 to 255) are available for external peripheral devices. external i/o pages have their own select pin ( ioms ). the dsp instruction set provides instructions for accessing i/o space. figure 2. core memory map at reset 0x00 0000 0x00 0fff 0x00 7fff 0x00 8fff 0x01 0000 0x40 0000 0x80 0000 0xc0 0000 0xff 0000 0xff 1000 0xff ffff 0x00 8000 0x00 1000 0x00 9000 0x00 ffff 0xff 0fff page 0 (64k) on-chip (0 wait state) external memory (4m ? 64k) pages 1 to 63 bank 0 (off-chip) ms0 page 255 (on-chip) external memory external memory pages 64 to 127 bank 1 (off-chip) pages 128 to 191 bank 2 (off-chip) pages 192 to 254 bank 0 (off-chip) ms1 ms2 ms3 external memory (4m ? 64k) block 0: 4k 24-bit ram reserved (28k) reserved (28k) block 1: 4k 16-bit ram block 2: 4k 24-bit pm rom unused on-chip memory (60k)
adsp-21990 ?6? rev. 0 boot memory space boot memory space consists of on e off-chip bank with 254 pages. the bms memory bank pin selects boot memory space. both the adsp-219x core and dma ca pable peripherals can access the dsp off-chip boot memory space. after reset, the dsp always starts executing instructions from the on-chip boot rom. bus request and bus grant the adsp-21990 can relinquish control of the data and address buses to an external device. when the external device requires access to the bus, it asserts the bus request ( br ) signal. the ( br ) signal is arbitrated with core and peripheral requests. external bus requests have the lowest priority. if no other internal request is pending, the external bus request will be granted. due to syn- chronizer and arbitration delays, bus grants will be provided with a minimum of three peripheral clock delays. the adsp-21990 will respond to the bus grant by: ? three-stating the data an d address buses and the ms3C0 , bms , ioms , rd , and wr output drivers. ? asserting the bus grant ( bg ) signal. the adsp-21990 will halt program execution if the bus is granted to an external device and an instruction fetch or data read/write request is made to ex ternal general-purpose or periph- eral memory spaces. if an instruction requires two external memory read accesses, the bus will not be granted between the two accesses. if an instruction requires an external memory read and an external memory write access, the bus may be granted between the two accesses. the exte rnal memory interface can be configured so that the core will have exclusive use of the interface. dma and bus requests will be granted. when the external device releases br , the dsp releases bg and continues program execution from the point at which it stopped. the bus request feature operates at all times, even while the dsp is booting and reset is active. the adsp-21990 asserts the bgh pin when it is ready to start another external port access, but is held off because the bus was previously granted. this mechanism can be extended to define more complex arbitration protocols for implementing more elaborate multimaster systems. dma controller the adsp-21990 has a dma co ntroller that supports automated data transfers with minimal overhead for the dsp core. cycle stealing dma transfers can occur between the adsp-21990 internal memory and any of its dma capable peripherals. additionally, dma transfers can be accomplished between any of the dma capabl e peripherals and external devices connected to the external memory interface. dma capable peripherals include the sport and spi ports, and adc control module. each individual dma capable peripheral has a dedicated dma channel. to desc ribe each dma sequence, the dma controller uses a set of parameters?called a dma descrip- tor. when successive dma sequences are needed, these dma descriptors can be linked or chained together, so the completion of one dma sequence auto initiates and starts the next sequence. dma sequences do not contend for bus access with the dsp core, instead dmas ?steal? cycles to access memory. all dma transfers use the dma bus shown in figure 1 on page 4 . because all of the peripheral s use the same bus, arbitra- tion for dma bus access is needed. the arbitration for dma bus access appears in table 1 . dsp peripherals architecture the adsp-21990 contains a number of special purpose, embedded control peripherals, wh ich can be seen in the func- tional block diagram on page 1. the adsp-21990 contains a high performance, 8-channel, 14-bit adc system with dual channel simultaneous sampling abilit y across four pairs of inputs. an internal precision voltage reference is also available as part of the adc system. in addition, a 3-phase, 16-bit, center based pwm generation unit can be used to produce high accuracy pwm signals with minimal processor overhead. the adsp-21990 also contains a flexible incremental encoder interface unit for position se nsor feedback; two adjustable frequency auxiliary pwm outputs, 16 lines of digital i/o; a 16-bit watchdog timer; three general-purpose timers, and an interrupt controller that manages all peripheral interrupts. figure 3. i/o memory map figure 4. boot memory map on-chip peripherals 16-bits off-chip peripherals 16-bits pages 0 to 31 1024 words/page 2 peripherals/page 0x00::0x000 0x20::0x000 0xff::0x3ff 0x1f::0x3ff pages 32 to 255 1024 words/page pages 1 to 254 64k words/page 0 x 0 1 0 0 0 0 0xfe 0000 off-chip boot memory 16-bits table 1. i/o bus arbitration priority dma bus master arbitration priority sport receive dma 0?highest sport transmit dma 1 adc control dma 2 spi receive/transmit dma 3 memory dma 4?lowest
?7? rev. 0 adsp-21990 finally, the adsp-21990 contains an integrated power-on-reset (por) circuit that can be used to generate the required reset signal for the device on power-on. the adsp-21990 has an external memory interface that is shared by the dsp core, the dm a controller, and dma capable peripherals, which include the adc, sport, and spi commu- nication ports. the external port consists of a 16-bit data bus, a 20-bit address bus, and control signals. the data bus is config- urable to provide an 8- or 16-bit interface to external memory. support for word packing lets th e dsp access 16- or 24-bit words from external memory regardless of the external data bus width. the memory dma controller lets the adsp-21990 move data and instructions from between memory spaces: internal-to- external, internal-to-internal, and external-to-external. on-chip peripherals can also use this controller for dma transfers. the embedded adsp-219x core can respond to up to seventeen interrupts at any given time: three internal (stack, emulator kernel, and power down), two external (emulator and reset), and twelve user defined (peripherals) interrupts. programmers assign each of the 32 peripheral interrup t requests to one of the 12 user defined interrupts. these assignments determine the priority of each peripheral for interrupt service. the following sections provide a functional overview of the adsp-21990 peripherals. serial peripheral interface (spi) port the serial peripheral interface (spi) port provides functionality for a generic configurable serial port interface based on the spi standard, which enable s the dsp to communicate with multiple spi compatible devices. key features of the spi port are: ? interface to host microcontroller or serial eeprom ? master or slave operation (3 -wire interface miso, mosi, sck) ? data rates to hclk 4 (16-bit baud rate selector) ? 8- or 16-bit transfer ? programmable clock phase and polarity ? broadcast mode ? 1 master, multiple slaves ? dma capability and dedicated interrupts ? pf0 can be used as slave select input line ? pf1?pf7 can be used as external slave select output spi is a 3-wire interface consis ting of 2 data pins (mosi and miso), one clock pin (sck), and a single slave select input ( spiss ) that is multiplexed with th e pf0 flag io line and seven slave select outputs (spisel1 to spisel7) that are multiplexed with the pf1 to pf7 flag io lines. the spiss input is used to select the adsp-21990 as a slave to an external master. the spisel1 to spisel7 outputs can be used by the adsp-21990 (acting as a master) to select/ena ble up to seven external slaves in a multidevice spi configuration. in a multimaster or a multi- device configuration, all mosi pi ns are tied together, all miso pins are tied together, and all sck pins are tied together. during transfers, the spi port simultaneously transmits and receives by serially shifting data in and out on the serial data line. the serial clock line synchronizes the shifting and sampling of data on the serial data line. in master mode, the dsp core performs the following sequence to set up and initiate spi transfers: 1. enables and configures the spi port operation (data size, and transfer format). 2. selects the target spi slave with the spiselx output pin (reconfigured programmable flag pin). 3. defines one or more dma descriptors in page 0 of i/o memory space (optional in dma mode only). 4. enables the spi dma engine and specifies transfer direction (optional in dma mode only). 5. in non dma mode only, reads or writes the spi port receive or transmit data buffer. the sck line generates the programmed clock pulses for simul- taneously shifting data out on mosi and shifting data in on miso. in dma mode only, transfers continue until the spi dma word count transitions from 1 to 0. in slave mode, the dsp core perf orms the following sequence to set up the spi port to receive data from a master transmitter: 1. enables and configures the spi slave port to match the operation parameters set up on the master (data size and transfer format) spi transmitter. 2. defines and generates a receive dma descriptor in page 0 of memory space to interrupt at the end of the data transfer (optional in dma mode only). 3. enables the spi dma engine for a receive access (optional in dma mode only). 4. starts receiving the data on the appropriate sck edges after receiving an spi chip select on the spiss input pin (reconfigured programmable flag pin) from a master. in dma mode only, reception continues until the spi dma word count transitions from 1 to 0. the dsp core could continue, by queuing up the next dma descriptor. slave mode transmit operation is similar, except that the dsp core specifies the data buffer in memory space from which to transmit data, generates and relinquishes control of the transmit dma descriptor, and begins filling the spi port data buffer. if the spi controller is not ready on time to transmit, it can transmit a ?zero? word. dsp serial port (sport) the adsp-21990 incorporates a complete synchronous serial port (sport) for serial and multiprocessor communications. the sport supports the following features: ? bidirectional: the sport has independent transmit and receive sections. ? double buffered: the sport section (both receive and transmit) has a data register for transferring data words to and from other parts of the processor and a register for shifting data in or out. the double buffering provides additional time to service the sport.
adsp-21990 ?8? rev. 0 ? clocking: the sport can use an external serial clock or generate its own in a wide range of frequencies down to 0 hz. ? word length: each sport sect ion supports serial data word lengths from three to si xteen bits that can be trans- ferred either msb first or lsb first. ? framing: each sport sectio n (receive and transmit) can operate with or without frame synchronization signals for each data-word; with internally generated or externally generated frame signals; with active high or active low frame signals; with either of two pulsewidths and frame signal timing. ? companding in hardware: each sport section can perform a law and law companding according to ccitt recommendation g.711. ? direct memory access with si ngle cycle overhead: using the built-in dma master, the sport can automatically receive and/or transmit multiple memory buffers of data with an overhead of only one dsp cycle per data-word. the on-chip dsp via a linked list of memory space resident dma descriptor blocks can configure transfers between the sport and memory space. this chained list can be dynamically allocated and updated. ? interrupts: each sport sect ion (receive and transmit) generates an interrupt upon completing a data-word transfer, or after transferring an entire buffer or buffers if dma is used. ? multichannel capability: the sport can receive and transmit data selectively from channels of a serial bit stream that is time division multiplexed into up to 128 channels. this is especially us eful for t1 interfaces or as a network communication scheme for multiple proces- sors. the sports also support t1 and e1 carrier systems. ? each sport channel (tx and rx) supports a dma buffer of up to eight, 16-bit transfers. ? the sport operates at a freque ncy of up to one-half the clock frequency of the hclk. ? the sport is capable of uart software emulation. analog-to-digital conversion system the adsp-21990 contains a fast, high accuracy, multiple input analog-to-digital conversion system with simultaneous sampling capabilities. this a/d conversion system permits the fast, accurate conversion of analog si gnals needed in high performance embedded systems. key features of the adc system are: ? 14-bit pipeline (6-stage pipeline) flash analog-to- digital converter ? 8 dedicated analog inputs ? dual channel simultaneous sampling capability ? programmable adc clock rate to maximum of hclk 4 ? first channel adc data valid approximately 375 ns after convst (at 20 msps) ? all 8 inputs converted in approximately 725 ns (at 20 msps) ? 2.0 v peak-to-peak input voltage range ? multiple conver t start sources ? internal or external voltage reference ? out of range detection ? dma capable transfers from adc to memory the adc system is based on a pipeline flash converter core, and contains dual input sample-and-h old amplifiers so that simulta- neous sampling of two input signals is supported. the adc system provides an analog inpu t voltage range of 2.0 vp-p and provides 14-bit performance with a clock rate of up to hclk 4. the adc system can be programmed to operate at a clock rate that is programmable from hclk 4 to hclk 30, to a maximum of 20 mhz (at 160 mhz cclk rate). the adc input structure supports 8 independent analog inputs; four of which are multiplexed in to one sample-and-hold amplifier (a_sha) and 4 of which are mult iplexed into the other sample- and-hold amplifier (b_sha). at the 20 mhz sampling rate, the first data value is valid approx- imately 375 ns after the convert start command. all 8 channels are converted in approximately 725 ns. the core of the adsp-21990 provid es 14-bit data such that the stored data values in the adc data registers are 14 bits wide. voltage reference the adsp-21990 contains an onboard band gap reference that can be used to provide a precise 1.0 v output for use by the a/d system and externally on the vref pin for biasing and level shifting functions. additionally, the adsp-21990 may be con- figured to operate with an extern al reference applied to the vref pin, if required. pwm generation unit key features of the 3-phase pwm generation unit are: ? 16-bit, center based pwm generation unit ? programmable pwm pulsewidth, with resolutions to 12.5 ns (at 80 mhz hclk rate) ? single/double update modes ? programmable dead time and switching frequency ? twos complement implementation permits smooth tran- sition into full on and full off states ? possibility to synchronize the pwm generation to an external synchronization ? special provisions for bdcm operation (crossover and output enable functions) ? wide variety of special switched reluctance (sr) operating modes ? output polarity and clock gating control ? dedicated asynchronous pwm shutdown signal ? multiple shutdown sources, independently for each unit
?9? rev. 0 adsp-21990 the adsp-21990 integrates a flexible and programmable, 3-phase pwm waveform generator that can be programmed to generate the required switchin g patterns to drive a 3-phase voltage source inverter for ac induction (acim) or permanent magnet synchronous (pmsm) motor control. in addition, the pwm block contains special functi ons that considerably simplify the generation of the required pwm switching patterns for control of the electronically commutated motor (ecm) or brushless dc motor (bdcm). tying a dedicated pin, pwmsr , to gnd, enables a special mode, for switched reluctance motors (srm). the six pwm output signals consist of three high side drive pins (ah, bh, and ch) and three low side drive signals pins (al, bl, and cl). the polarity of the generated pwm signals may be set via hardware by the pwmpol input pin, so that either active hi or active lo pwm patterns can be produced. the switching frequency of the generated pwm patterns is pro- grammable using the 16-bit pwmtm register. the pwm generator is capable of operating in two distinct modes, single update mode or double update mo de. in single update mode the duty cycle values are programmable only once per pwm period, so that the resultant pwm patt erns are symmetrical about the midpoint of the pwm period. in the double update mode, a second updating of the pwm registers is implemented at the midpoint of the pwm period. in this mode, it is possible to produce asymmetrical pwm patterns. that produce lower harmonic distortion in 3-phase pwm inverters. auxiliary pwm generation unit key features of the auxiliary pwm generation unit are: ? 16-bit, programmable frequency, programmable duty cycle pwm outputs ? independent or offset operating modes ? double buffered control of duty cycle and period registers ? separate auxiliary pwm synchronization signal and asso- ciated interrupt (can be used to trigger adc convert start) ? separate auxiliary pwm shutdown signal ( auxtrip ) the adsp-21990 integrates a 2-channel, 16-bit, auxiliary pwm output unit that can be programmed with variable frequency, variable duty cycle values and may operate in two different modes, independent mode or offs et mode. in independent mode, the two auxiliary pwm generators are completely independent and separate switching frequencies and duty cycles may be pro- grammed for each auxiliary pwm output. in offset mode the switching frequency of the two signals on the aux0 and aux1 pins is identical. bit 4 of the auxctrl register places the auxiliary pwm channel pair in independent or offset mode. the auxiliary pwm generation unit provides two chip output pins, aux0 and aux1 (on which the switching signals appear) and one chip input pin, auxtrip , which can be used to shut down the switching signals?for example, in a fault condition. encoder interface unit the adsp-21990 incorporates a powerful encoder interface block to incremental shaft encoders that are often used for position feedback in high performance motion control systems. ? quadrature rates to 53 mhz (at 80 mhz hclk rate) ? programmable filtering of all encoder input signals ? 32-bit encoder counter ? variety of hardware and software reset modes ? two registration inputs to latch eiu count value with corresponding registration interrupt ? status of a/b signals latched with reading of eiu count value ? alternative frequency and direction mode ? single north marker mode ? count error monitor function with dedicated error interrupt ? dedicated 16-bit loop timer with dedicated interrupt ? companion encoder event (1 ? t) timer unit the encoder interface unit (eiu) includes a 32-bit quadrature up/down counter, programmable input noise filtering of the encoder input signals and the zero markers, and has four dedicated chip pins. the quadrature encoder signals are applied at the eia and eib pins. alternatively, a frequency and direction set of inputs may be applied to the eia and eib pins. in addition, two north marker/strobe inputs are provided on pins eiz and eis. these inputs may be used to latch the contents of the encoder quadrature counter into dedicated registers, eizlatch and eislatch, on the occurrence of external events at the eiz and eis pins. these events may be programmed to be either rising edge only (latch event) or rising edge if the encoder is moving in the forward direction and falling edge if the encoder is moving in the reverse direction (software latched north marker functionality). the encoder interface unit incorporates programmable noise filtering on the four encoder inputs to prevent spurious noise pulses from adversely affecting the operation of the quadrature counter. the encoder interface unit operates at a clock frequency equal to the hclk rate. the encoder interface unit operates correctly with encoder signals at frequencies of up to 13.25 mhz at the 80 mhz hclk rate, corresponding to a maximum quadrature frequency of 53 mhz (assuming an ideal quadrature relationship between the input eia and eib signals). the eiu may be programmed to use the north marker on eiz to reset the quadrature encoder in hardware, if required. alternatively, the north marker can be ignored, and the encoder quadrature counter is reset according to the contents of a maximum count register, eiumaxcnt. there is also a ?single north marker? mode available in which the encoder quadrature counter is reset only on the first north marker pulse.
adsp-21990 ?10? rev. 0 the encoder interface unit can also be made to implement some error checking functions. if an encoder count error is detected (due to a disconnected encoder line, for example), a status bit in the eiustat register is set, and an eiu count error interrupt is generated. the encoder interface unit of the adsp-21990 contains a 16-bit loop timer that consists of a timer register, period register and scale register so that it can be programmed to time out and reload at appropriate intervals. when this loop timer times out, an eiu loop timer timeout interrupt is generated. this interrupt could be used to control the timing of speed and position control loops in high performance drives. the encoder interface unit also includes a high performance encoder event timer (eet) block that permits the accurate timing of successive events of the encoder inputs. the eet can be pro- grammed to time the duration between up to 255 encoder pulses and can be used to enhance velocity estimation, particularly at low speeds of rotation. flag i/o (fio) peripheral unit the fio module is a generic para llel i/o interface that supports sixteen bidirectional multifunct ion flags or general-purpose digital i/o signals (pf15?0). all sixteen flag bits can be individually configured as an input or output based on the content of the direction (dir) register, and can also be used as an interrupt source for one of two fio interrupts. when configured as input, the input signal can be programmed to set the flag on either a level (level sensitive input/interrupt) or an edge (edge sensitive input/interrupt). the fio module can also be used to generate an asynchronous unregistered wake-up signal fio_wakeup for dsp core wake up after power-down. the fio lines, pf7?1 ca n also be configured as external slave select outputs for the spi communications port, while pf0 can be configured to act as a slave select input. the fio lines can be configured to act as a pwm shutdown source for the 3-phase pwm generation unit of the adsp-21990. watchdog timer the adsp-21990 integrates a watchdog timer that can be used as a protection mechanism against unintentional software events. it can be used to cause a comple te dsp and peripheral reset in such an event. the watchdog timer consists of a 16-bit timer that is clocked at the external clock rate (clkin or crystal input frequency). in order to prevent an unwanted timeout or reset, it is necessary to periodically write to the watchdog timer register. during abnormal system operation, the watchdog count will eventually decrement to 0 and a watchdog timeout will occur. in the system, the watchdog timeout will cause a full reset of the dsp core and peripherals. general-purpose timers the adsp-21990 contains a general-purpose timer unit that contains three identical 32-bit timers. the three programmable interval timers (timer0, timer1, and timer2) generate periodic interrupts. each timer can be independently set to operate in one of three modes: ? pulse waveform generation (pwm_out) mode ? pulsewidth count/capture (wdth_cap) mode ? external event watchdog (ext_clk) mode each timer has one bidirectiona l chip pin, tmr2-0. for each timer, the associated pin is configured as an output pin in pwm_out mode and as an input pin in wdth_cap and ext_clk modes. interrupts the interrupt controller lets th e dsp respond to 17 interrupts with minimum overhead. the dsp core implements an interrupt priority scheme as shown in table 2 . applications can use the unassigned slots for software and peripheral interrupts. the peripheral interrupt controller is used to assign the various peripheral interrupts to the 12 us er assignable interrupts of the dsp core. there is no assigned priority fo r the peripheral interrupts after reset. to assign the peripheral interrupts a different priority, applications write the new priority to their corresponding control bits (determined by their id) in the interrupt priority control register. interrupt routines can either be ne sted with higher priority inter- rupts taking precedence or processed sequentially. interrupts can be masked or unmasked with the imask register. individual interrupt requests are logically anded with the bits in imask; the highest priority unmasked in terrupt is then selected. the emulation, power down, and reset interrupts are nonmaskable with the imask register, but software can use the dis int instruction to mask the power-down interrupt. the interrupt control (icntl) register controls interrupt nesting and enables or disables interrupts globally. the irptl register is used to force and clear interrupts. on-chip stacks preserve the processor status and are automatically main- tained during interrupt handling. to support interrupt, loop, and subroutine nesting, the pc stack is 33 levels deep, the loop stack is 8 levels deep, and the status stack is 16 levels deep. to prevent stack overflow, the pc stack can generate a stack level interrupt if the pc stack falls below 3 locations full or rises above 28 locations full. the following instructions global ly enable or disable interrupt servicing, regardless of the state of imask. ena int; dis int; at reset, interrupt servicing is disabled. for quick servicing of interrupts, a secondary set of dag and computational registers exist. switching between the primary and secondary registers lets programs quickly service interrupts, while preserving the state of the dsp.
?11? rev. 0 adsp-21990 peripheral interrupt controller the peripheral interrupt controller is a dedicated peripheral unit of the adsp-21990 (accessed vi a io mapped registers). the peripheral interrupt controller manages the connection of up to 32 peripheral interrupt requests to the dsp core. for each peripheral interrupt sour ce, there is a unique 4-bit code that allows the user to assign th e particular peripheral interrupt to any one of the 12 user assignable interrupts of the embedded adsp-219x core. therefore, the peripheral interrupt controller of the adsp-21990 contains eight, 16-bit interrupt priority registers (interrupt priority register 0 (ipr0) to interrupt priority register 7 (ipr7)). each interrupt priority register contains a four 4-bit codes; one specifically assigned to each peri pheral interrupt. the user may write a value between 0x0 and 0xb to each 4-bit location in order to effectively connect the particul ar interrupt source to the cor- responding user assignable in terrupt of the adsp-219x core. writing a value of 0x0 connects th e peripheral interrupt to the usr0 user assignable interrup t of the adsp-219x core while writing a value of 0xb connects th e peripheral interrupt to the usr11 user assignable interrupt. the core interrupt usr0 is the highest priority user interrupt, while usr11 is the lowest priority. writing a value between 0xc and 0xf effectively disables the peripheral interrupt by not conn ecting it to any adsp-219x core interrupt input. the user may a ssign more than one peripheral interrupt to any given adsp-219x core interrupt. in that case, the burden is on the user software in the interrupt vector table to determine the exact interrupt source through reading status bits. this scheme permits the user to assign the number of specific interrupts that are unique to th eir application to the interrupt scheme of the adsp-219x core. the user can then use the existing interrupt priority control scheme to dynamically control the priorities of the 12 core interrupts. low power operation the adsp-21990 has four low power options that significantly reduce the power dissipation when the device operates under standby conditions. to enter any of these modes, the dsp executes an idle instruction. the adsp-21990 uses the con- figuration of the pd, stck, and stall bits in the pllctl register to select between the low power modes as the dsp executes the idle instruction. depending on the mode, an idle shuts off clocks to different parts of the dsp in the different modes. the low power modes are: ? idle ? power-down core ? power-down core/peripherals ? power-down all idle mode when the adsp-21990 is in idle mode, the dsp core stops executing instructions, retains the contents of the instruction pipeline, and waits for an interrupt. the core clock and peripheral clock continue running. to enter idle mode, the dsp can execute the idle instruction anywhere in code. to exit idle mode, the dsp responds to an interrupt and (after two cycles of latency) resumes executing instructions. power-down core mode when the adsp-21990 is in power-down core mode, the dsp core clock is off, but the dsp retains the contents of the pipeline and keeps the pll running. the pe ripheral bus keeps running, letting the peripherals receive data. to exit power-down core mode, the dsp responds to an interrupt and (after two cycles of latency) resumes executing instructions. power-down core/peripherals mode when the adsp-21990 is in power-down core/peripherals mode, the dsp core clock and peripheral bus clock are off, but the dsp keeps the pll running. the dsp does not retain the contents of the instruction pipeline.the peripheral bus is stopped, so the peripherals cannot receive data. to exit power-down core/perip herals mode, the dsp responds to an interrupt and (after five to six cycles of latency) resumes executing instructions. table 2. interrupt priorities/addresses interrupt imask/ irptl vector address emulator (nmi) ?highest priority na na reset (nmi) 0 0x00 0000 power down (nmi) 1 0x00 0020 loop and pc stack 2 0x00 0040 emulation kernel 3 0x00 0060 user assigned interrupt (usr0) 4 0x00 0080 user assigned interrupt (usr1) 5 0x00 00a0 user assigned interrupt (usr2) 6 0x00 00c0 user assigned interrupt (usr3) 7 0x00 00e0 user assigned interrupt (usr4) 8 0x00 0100 user assigned interrupt (usr5) 9 0x00 0120 user assigned interrupt (usr6) 10 0x00 0140 user assigned interrupt (usr7) 11 0x00 0160 user assigned interrupt (usr8) 12 0x00 0180 user assigned interrupt (usr9) 13 0x00 01a0 user assigned interrupt (usr10) 14 0x00 01c0 user assigned interrupt (usr11) ?lowest priority 15 0x00 01e0
adsp-21990 ?12? rev. 0 power-down all mode when the adsp-21990 is in power-down all mode, the dsp core clock, the peripheral clock, and the pll are all stopped. the dsp does not retain the contents of the instruction pipeline. the peripheral bus is stopped, so th e peripherals cannot receive data. to exit power-down core/peripherals mode, the dsp responds to an interrupt and (after 500 cycles to re-stabilize the pll) resumes executing instructions. clock signals the adsp-21990 can be clocked by a crystal oscillator or a buffered, shaped clock derived from an external clock oscillator. if a crystal oscillator is used, the crystal should be connected across the clkin and xtal pins, with two capacitors connected as shown in figure 5 . capacitor values are dependent on crystal type and should be specified by the crystal manufac- turer. a parallel resonant, fundamental frequency, microprocessor grade crystal should be used for this configuration. if a buffered, shaped clock is used, this external clock connects to the dsp clkin pin. clkin input cannot be halted, changed, or operated below the specified frequency during normal operation. this clock sign al should be a ttl compatible signal. when an external clock is used, the xtal input must be left unconnected. the dsp provides a user programmable 1 to 32 multiplica- tion of the input clock, including some fractional values, to support 128 external to internal (dsp core) clock ratios. the bypass pin, and msel6?0 and df bits, in the pll configu- ration register, decide the pll multiplication factor at reset. at run time, the multiplication factor can be controlled in software. to support input clocks greater that 100 mhz, the pll uses an additional bit (df). if the input clock is greater than 100 mhz, df must be set. if the input clock is less than 100 mhz, df must be cleared. for clock multiplier settings, see the adsp-2199x mixed signal dsp controller hardware reference . the peripheral clock is supplied to the clkout pin. all on-chip peripherals for the adsp-21990 operate at the rate set by the peripheral clock. th e peripheral clock (hclk) is either equal to the core clock rate or one half the dsp core clock rate (cclk). this selection is controlled by the iosel bit in the pllctl register. the maximum core clock is 160 mhz for the adsp-21990bst and 150 mhz for the adsp- 21990bbc.the maximum peripheral clock is 80 mhz for the adsp-21990bst and 75 mhz for the ADSP-21990BBC?the combination of the input clock and core/peripheral clock ratios may not exceed these limits. reset and power-on reset (por) the reset pin initiates a complete hardware reset of the adsp- 21990 when pulled low. the reset signal must be asserted when the device is powered up to assure proper initialization. the adsp-21990 contains an integrated power-on reset (por) circuit that provides an output reset signal, por , from the adsp- 21990 on power-up and if the power supply voltage falls below the threshold level. the adsp-21990 may be reset from an external source using the reset signal, or alternatively, the internal power-on reset circuit may be used by connecting the por pin to the reset pin. during power-up the reset line must be activated for long enough to allow the dsp core?s internal clock to stabilize. the power-up sequence is defined as the total time required for the crystal oscillator to stabilize after a valid vdd is applied to the processor an d for the internal phase-locked loop (pll) to lock onto the specific crystal frequency. a minimum of 512 cycles will ensure that the pll has locked (this does not include the crystal oscillator start-up time). the reset input contains some hysteresis. if an rc circuit is used to generate the reset signal, the circuit should use an external schmitt trigger. the master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and resets all registers to their default values (where applicable). when reset is released, if there is no pending bus request, program control jumps to the location of the on-chip boot rom (0xff0000) and the booting sequence is performed. power supplies the adsp-21990 has separate power supply connections for the internal (v ddint ) and external (v ddext ) power supplies. the internal supply must meet the 2.5 v requirement. the external supply must be connected to a 3.3 v supply. all external supply pins must be connected to the same supply. the ideal power-on sequence for the dsp is to provide power-up of all supplies simul- taneously. if there is going to be some delay in power-up between the supplies, provide v dd first, then v dd_io . figure 5. external crystal connections clkin xtal adsp-2199x
?13? rev. 0 adsp-21990 booting modes the adsp-21990 supports a numbe r of different boot modes that are controlled by the three dedicated hardware boot mode control pins (bmode2, bmode1, and bmode0). the use of three boot mode control pins means that up to eight different boot modes are possible. of thes e only five modes are valid on the adsp-21990. the adsp-21990 exposes the boot mechanism to software control by providing a nonmaskable boot interrupt that vectors to the start of the on-chip rom memory block (at address 0xff0000). a boot interrupt is automatically initiated following either a hardware initiated reset, via the reset pin, or a software initiated reset, via writing to the software reset register. following either a hardware or a software reset, execution always starts from the boot rom at address 0xff0000, irrespective of the settings of the bmode2, bmode1, and bmode0 pins. the dedicated bmode2, bmode1, and bmode0 pins are sampled at hardware reset. the particular boot mode for the adsp-21990 associated with the settings of the bmode2, bmode1, bmode0 pins is defined in table 3 . instruction set description the adsp-21990 assembly langua ge instruction set has an algebraic syntax that was designed for ease of coding and read- ability. the assembly language, wh ich takes full advantage of the unique architecture of the processor, offers the following benefits: ? adsp-219x assembly language sy ntax is a superset of and source code compatible (excep t for two data registers and dag base address registers) with adsp-21xx family syntax. it may be necessary to restructure adsp-21xx programs to accommodat e the adsp-21990 unified memory space and to conform to its interrupt vector map. ? the algebraic syntax eliminates the need to remember cryptic assembler mnemonics. for example, a typical arithmetic add instruction, such as ar = ax0 + ay0, resembles a simple equation. ? every instruction, but two, assembles into a single, 24-bit word that can execute in a si ngle instruction cycle. the exceptions are two dual word instructions. one writes 16-bit or 24-bit immediate data to memory, and the other is an absolute jump/call with the 24-bit address specified in the instruction. ? multifunction instructions allo w parallel execution of an arithmetic, mac, or shift instruction with up to two fetches or one write to processor memory space during a single instruction cycle. ? program flow instructions support a wider variety of con- ditional and unconditional jumps/calls and a larger set of conditions on which to base execution of conditional instructions. development tools the adsp-21990 is supported with a complete set of crosscore? software and hardware development tools, including analog devices emulators and visualdsp++? devel- opment environment. the emulator hardware that supports other adsp-219x dsps also fully emulates the adsp-21990. the visualdsp++ project management environment lets pro- grammers develop and debug an application. this environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/lib rary builder), a linker, a loader, a cycle-accurate instruction-level simulator, a c/c++ compiler, and a c/c++ runtime library that includes dsp and mathemat- ical functions. a key point for these tools is c/c++ code efficiency. the compiler has been developed for efficient transla- tion of c/c++ code to dsp asse mbly. the dsp has architectural features that improve the efficiency of compiled c/c++ code. the visualdsp++ debugger has a number of important features. data visualization is enhanced by a plotting package that offers a significant level of flexibility. this graphical representation of user data enables the programmer to quickly determine the per- formance of an algorithm. as algorithms grow in complexity, this capability can have significant influence on the design develop- ment schedule, increasing productivity. statistical profiling enables the programmer to nonint rusively poll the processor as it is running the program. this feature, unique to visualdsp++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteris- tics of the program. essentially, the developer can identify bottlenecks in software quickly and efficiently. by using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. table 3. summary of boot modes boot mode bmode2 bmode1 bmode0 function 0 0 0 0 illegal ? reserved 1 0 0 1 boot from external 8-bit memory over emi 2 0 1 0 execute from external 8-bit memory 3 0 1 1 execute from external 16-bit memory 4 1 0 0 boot from spi 4k bits 5 1 0 1 boot from spi > 4k bits 6 1 1 0 illegal ? reserved 7 1 1 1 illegal ? reserved
adsp-21990 ?14? rev. 0 debugging both c/c++ and as sembly programs with the visualdsp++ debugger, programmers can: ? view mixed c/c++ and assembly code (interleaved source and object information). ? insert breakpoints. ? set conditional breakpoints on registers, memory, and stacks. ? trace instruction execution. ? perform linear or statistical profiling of program execution. ? fill, dump, and graphically pl ot the contents of memory. ? perform source level debugging. ? create custom debugger windows. the visualdsp++ idde lets programmers define and manage dsp software development. its dialog boxes and property pages let programmers configure and manage all of the adsp-219x development tools, including the color syntax highlighting in the visualdsp++ editor. this capability permits programmers to: ? control how the development tools process inputs and generate outputs. ? maintain a one-to-one correspondence with the command line switch es of the tool. the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored speci fically to address the memory and timing constraints of dsp programming. these capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. the vdk features include threads, critical and unscheduled regions, semaphores, events, and device flags. the vdk also supports priori ty-based, preemptive, coopera- tive, and time-sliced scheduling approaches. in addition, the vdk was designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ devel- opment environment, but can also be used via standard command line tools. when the vdk is used, the development environment assists the develope r with many error-prone tasks and assists in managing system resources, automating the gener- ation of various vdk based objects, and visualizing the system state, when debugging an application that uses the vdk. vcse is analog devices techno logy for creating, using, and reusing software components (independent modules of substan- tial functionality) to quickly and reliably assemble software applications. download components from the web and drop them into the application. pu blish component archives from within visualdsp++. vcse su pports component implementa- tion in c/c++ or assembly language. use the expert linker to visually manipulate the placement of code and data on the embedded system. view memory utilization in a color-coded graphical form, easily move code and data to different areas of the dsp or exte rnal memory with the drag of the mouse, examine run time stac k and heap usage. the expert linker is fully compatible with existing linker definition file (ldf), allowing the developer to move between the graphical and textual environments. analog devices dsp emulators use the ieee 1149.1 jtag test access port of the adsp-21990 pr ocessor to monitor and control the target board processor duri ng emulation. the emulator provides full speed emulation, a llowing inspection and modifica- tion of memory, registers, and processor stacks. nonintrusive in-circuit emulation is assured by the use of the processor jtag interface?target system loading and timing are not affected by the emulator. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the adsp-219x processor family. hardware tools include adsp-219x dsp pc plug-in cards. third party software tools include dsp librari es, real-time operating systems, and block diagram design tools. designing an emulator-compatible dsp board the analog devices family of emulators are tools that every dsp developer needs to test and debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. the emulator uses the tap to access the internal features of the dsp, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the dsp must be halted to send data and commands, but once an operation has been completed by the emulator, the ds p system is set running at full speed with no impact on system timing. to use these emulators, the target board must include a header that connects the dsp jtag port to the emulator. for details on target board design issues including mechanical layout, single processor connectio ns, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the ee-68: analog devices j tag emulation technical reference on the analog devices website ( www.analog.com )?use site search on ?ee-68.? this document is updated regularly to keep pace with improvements to emulator support. additional information this data sheet provides a general overview of the adsp-21990 architecture and functionality. for detailed information on the adsp-21990 embedded dsp core architecture, instruction set, communications ports and embedded control peripherals, refer to the adsp-2199x mixed signal dsp controller hardware reference . pin function descriptions adsp-21990 pin definitions are listed in table 4 . all adsp- 21990 inputs are asynchronous and can be asserted asynchro- nously to clkin (or to tck for trst ). unused inputs should be tied or pulled to v ddext or gnd, except for addr21?0, data15?0, pf7-0, and inputs that have internal pull-up or pull-down resistors ( trst , bmode0, bmode1, bmode2, bypass, tck, tms, tdi, pwmpol, pwmsr , and reset )?these pins can be left floating. these
?15? rev. 0 adsp-21990 pins have a logic level hold circuit that prevents input from floating internally. pwmtrip has an internal pull-down, but should not be left floating to avoid unnecessary pwm shutdowns. the following symbols appear in the type column of table 4 : g = ground, i = input, o = output, p = power supply, b = bidirectional, t = three-state, d = digital, a = analog, ckg = clock generation pin, pu = internal pull-up, and pd = internal pull-down. table 4. pin descriptions pin type function a19-0 d, ot external port address bus d15-0 d, bt external port data bus rd d, ot external port read strobe wr d, ot external port write strobe ack d, i external port access ready acknowledge br d, i, pu external port bus request bg d, o external port bus grant bgh d, o external port bus grant hang ms0 d, ot external port memory select strobe 0 ms1 d, ot external port memory select strobe 1 ms2 d, ot external port memory select strobe 2 ms3 d, ot external port memory select strobe 3 ioms d, ot external port io space select strobe bms d, ot external port boot memory select strobe clkin d, i, ckg clock input/osci llator input/crystal connection 0 xtal d, o, ckg oscillator output/ crystal connection 1 clkout d, o clock output (hclk) bypass d, i, pu pll bypass mode select reset d, i, pu processor reset input por d, o power on reset output bmode2 d, i, pu boot mode select input 2 bmode1 d, i, pd boot mode select input 1 bmode0 d, i, pu boot mode select input 0 tck d, i jtag test clock tms d, i, pu jtag test mode select tdi d, i, pu jtag test data input tdo d, ot jtag test data output trst d, i, pu jtag test reset input emu d, ot, pu emulation status vin0 a, i adc input 0 vin1 a, i adc input 1 vin2 a, i adc input 2 vin3 a, i adc input 3 vin4 a, i adc input 4 vin5 a, i adc input 5 vin6 a, i adc input 6 vin7 a, i adc input 7 ashan a, i inverting sha_a input bshan a, i inverting sha_b input capt a, o noise reduction pin capb a, o noise reduction pin vref a, i, o voltage reference pin (mode selected by state of sense) sense a, i voltage re ference select pin cml a, o common-mode level pin convst d, i adc convert start input pf15 d, bt, pd general-purpose io15 pf14 d, bt, pd general-purpose io14 pf13 d, bt, pd general-purpose io13
adsp-21990 ?16? rev. 0 pf12 d, bt, pd general-purpose io12 pf11 d, bt, pd general-purpose io11 pf10 d, bt, pd general-purpose io10 pf9 d, bt, pd general-purpose io9 pf8 d, bt, pd general-purpose io8 pf7/spisel7 d, bt, pd general-purpose io7 / spi slave select output 7 pf6/spisel6 d, bt, pd general-purpose io6 / spi slave select output 6 pf5/spisel5 d, bt, pd general-purpose io5 / spi slave select output 5 pf4/spisel4 d, bt, pd general-purpose io4 / spi slave select output 4 pf3/spisel3 d, bt, pd general-purpose io3 / spi slave select output 3 pf2/spisel2 d, bt, pd general-purpose io2 / spi slave select output 2 pf1/spisel1 d, bt, pd general-purpose io1 / spi slave select output 1 pf0/ spiss d, bt, pd general-purpose io0 / spi slave select input 0 sck d, bt spi clock miso d, bt spi master in slave out data mosi d, bt spi master out slave in data dt d, ot sport data transmit dr d, i sport data receive rfs d, bt sport receive frame sync tfs d, bt sport transmit frame sync tclk d, bt sport transmit clock rclk d, bt sport receive clock eia d, i encoder a channel input eib d, i encoder b channel input eiz d, i encoder z channel input eis d, i encoder s channel input aux0 d, o auxiliary pwm channel 0 output aux1 d, o auxiliary pwm channel 1 output auxtrip d, i, pd auxiliary pwm shutdown pin tmr2 d, bt timer 0 input/output pin tmr1 d, bt timer 1 input/output pin tmr0 d, bt timer 2 input/output pin ah d, o pwm channel a hi pwm al d, o pwm channel a lo pwm bh d, o pwm channel b hi pwm bl d, o pwm channel b lo pwm ch d, o pwm channel c hi pwm cl d, o pwm channel c lo pwm pwmsync d, bt pwm synchronization pwmpol d, i, pu pwm polarity pwmtrip d, i, pd pwm trip pwmsr d, i, pu pwm sr mode select avdd (2 pins) a, p analog supply voltage avss (2 pins) a, g analog ground vddint (6 pins) d, p digital internal supply vddext (10 pins) d, p digital external supply gnd (16 pins) d, g digital ground table 4. pin descriptions (continued) pin type function
?17? rev. 0 adsp-21990 specifications specifications subject to change without notice. recommended operating conditions?ADSP-21990BBC parameter min typ max unit v ddint internal (core) supply voltage 2.375 2.5 2.625 v v ddext external (i/o) supply voltage 3.135 3.3 3.465 v avdd analog supply voltage 2.375 2.5 2.625 v cclk dsp instruction ra te, core clock 0 150 mhz hclk 1, 2 peripheral clock rate 0 75 mhz clkin 3 input clock frequency 0 150 mhz t junc 4 silicon junction temperature +140oc oc t amb ambient operating temperature ?40oc +85oc oc 1 the hclk frequency may be made to appear at the dedicated clkout pin of the device. fo r low power operation, however, the clkou t pin can be disabled. 2 the peripherals operate at the hclk rate, which may be selected to be equal to cclk or cclk 2, up to a maximum of a 75 mhz hclk for the ADSP-21990BBC. 3 in order to attain the correct cclk and hclk values, the input clock frequency or crystal freq uency depends on the internal ope ration of the clock generation pll circuit and the associated frequency ratio. 4 the maximum junction temperature is limited to 140c in order to meet all of the electrical specifications. it is ultimately th e responsibility of the user to ensure that the power dissipation of the adsp -21990 (including all dc an d ac loads) is such that the maximum junction temperatu re limit of 140c is not exceeded. recommended operating conditions?adsp-21990bst parameter min typ max unit v ddint internal (core) supply voltage 2.375 2.5 2.625 v v ddext external (i/o) supply voltage 3.135 3.3 3.465 v avdd analog supply voltage 2.375 2.5 2.625 v cclk dsp instruction ra te, core clock 0 160 mhz hclk 1, 2 peripheral clock rate 0 80 mhz clkin 3 input clock frequency 0 160 mhz t junc 4 silicon junction temperature +140oc oc t amb ambient operating temperature ?40oc +85oc oc 1 the hclk frequency may be made to appear at the dedicated clkout pin of the device. fo r low power operation, however, the clkou t pin can be disabled. 2 the peripherals operate at the hclk rate, which may be selected to be equal to cclk or cclk 2, up to a maximum of an 80 mhz hclk for the adsp-21990bst. 3 in order to attain the correct cclk and hclk values, the input clock frequency or crystal freq uency depends on the internal ope ration of the clock generation pll circuit and the associated frequency ratio. 4 the maximum junction temperature is limited to 140c in order to meet all of the electrical specifications. it is ultimately th e responsibility of the user to ensure that the power dissipation of the adsp-21990 (including all dc and ac loads) is such th at the maximum junction temperatu re limit of 140c is not exceeded.
adsp-21990 ?18? rev. 0 electrical characteristics?ADSP-21990BBC parameter test conditions min typ max unit v ih high level input voltage 1 @ v ddext = maximum 2.0 v ddext v v ih high level input voltage 2 @ v ddext = maximum 2.2 v ddext v v il high level input voltage 1, 2 @ v ddext = minimum 0.8 v v oh high level output voltage 3 @ v ddext = minimum, i oh = ?0.5 ma 2.4 v v ol low level output voltage 3 @ v ddext = minimum, i ol = 2.0 ma 0.4 v i ih high level input current 4 @ v ddint = maximum, v in = 3.6 v 10 a i ih high level input current 5 @ v ddint = maximum, v in = 3.6 v 150 a i ih high level input current 6 @ v ddint = maximum, v in = 3.6 v 10 a i il low level input current @ v ddint = maximum, v in = 0 v 10 a i il low level input current @ v ddint = maximum, v in = 0 v 10 a i il low level input current @ v ddint = maximum, v in = 0 v 150 a i ozh three-state leakage current 7 @ v ddint = maximum, v in = 3.6 v 10 a i ozl three-state leakage current 7 @ v ddint = maximum, v in = 0 v 10 a c i input pin capacitance f in = 1 mhz 10 pf c o output pin capacitance f in = 1 mhz 10 pf i dd-peak supply current (internal) 8, 9 300 350 ma i dd-typ supply current (internal) 8 250 290 ma i dd-idle supply current (idle) 8 230 285 ma i dd-stopclk supply current (power-down) 8, 10 130 190 ma i dd-stopall supply current (power-down) 8, 11 15 75 ma i dd-pdown supply current (power-down) 8, 12 10 60 ma i avdd analog supply current 13 55 65 ma i avdd-adcof f analog supply current 12 20 35 ma 1 applies to all input and bidirectional pins. 2 applies to input pins clkin, reset , trst . 3 applies to all output and bidirectional pins. 4 applies to all input only pins. 5 applies to input pins with internal pull-down. 6 applies to input pins with internal pull-up. 7 applies to three-stateable pins. 8 the i dd supply currents are affected by the operating frequency of the device. the guaranteed numbers are based on an assumed cclk = 1 50 mhz, hclk = 75 mhz for th e ADSP-21990BBC. i dd refers only to the current consumption on the internal power supply lines (v ddint ). the current consumption at the i/o on the v ddext power supply is very much dependent on the parti cular connection of the device in the final system. 9 i dd-peak represents worst-case processor operation and is not sustainable under normal application conditions. actual internal power me asurements made using typical applications are less than specified. measured at v ddint = maximum. 10 idle denotes the current consumption during execution of the idle instruction. measured at v ddint = maximum. 11 i dd-pdown represents the processor operation in full power-down mode with both core and peripheral clocks disabled. measured at v ddint = maximum. 12 i avdd represents the power consumption of the analog system. measured at avdd = maximum. 13 the responsibility lies with the user to ensure that the device is operated in such a manner that the maximum allowable junctio n temperature is not exceeded.
?19? rev. 0 adsp-21990 electrical characteristics?adsp-21990bst parameter test conditions min typ max unit v ih high level input voltage 1 @ v ddext = maximum 2.0 v ddext v v ih high level input voltage 2 @ v ddext = maximum 2.2 v ddext v v il high level input voltage 1, 2 @ v ddext = minimum 0.8 v v oh high level output voltage 3 @ v ddext = minimum, i oh = ?0.5 ma 2.4 v v ol low level output voltage 3 @ v ddext = minimum, i ol = 2.0 ma 0.4 v i ih high level input current 4 @ v ddint = maximum, v in = 3.6 v 10 a i ih high level input current 5 @ v ddint = maximum, v in = 3.6 v 150 a i ih high level input current 6 @ v ddint = maximum, v in = 3.6 v 10 a i il low level input current @ v ddint = maximum, v in = 0 v 10 a i il low level input current @ v ddint = maximum, v in = 0 v 10 a i il low level input current @ v ddint = maximum, v in = 0 v 150 a i ozh three-state leakage current 7 @ v ddint = maximum, v in = 3.6 v 10 a i ozl three-state leakage current 7 @ v ddint = maximum, v in = 0 v 10 a c i input pin capacitance f in = 1 mhz 10 pf c o output pin capacitance f in = 1 mhz 10 pf i dd-peak supply current (internal) 8, 9 325 375 ma i dd-typ supply current (internal) 8 275 320 ma i dd-idle supply current (idle) 8 250 300 ma i dd-stopclk supply current (power-down) 8, 10 140 175 ma i dd-stopall supply current (power-down) 8, 11 25 55 ma i dd-pdown supply current (power-down) 8, 12 15 45 ma i avdd analog supply current 13 55 65 ma i avdd-adcof f analog supply current 12 20 35 ma 1 applies to all input and bidirectional pins. 2 applies to input pins clkin, reset , trst . 3 applies to all output and bidirectional pins. 4 applies to all input only pins. 5 applies to input pins with internal pull-down. 6 applies to input pins with internal pull-up. 7 applies to three-stateable pins. 8 the i dd supply currents are affected by the operating frequency of the device. the guaranteed numbers are based on an assumed cclk = 1 60 mhz, hclk = 80 mhz for the adsp-21990bst. i dd refers only to the current consumption on the internal power supply lines (v ddint ). the current consumption at the i/o on the v ddext power supply is very much dependent on the parti cular connection of the device in the final system. 9 i dd-peak represents worst-case processor operation and is not sustainable under normal application conditions. actual internal power me asurements made using typical applications are less than specified. measured at v ddint = maximum. 10 idle denotes the current consumption during execution of the idle instruction. measured at v ddint = maximum. 11 i dd-pdown represents the processor operation in full power-down mode wi th both core and peripheral clocks disabled. measured at v ddint = maximum. 12 i avdd represents the power consumption of the analog system. measured at avdd = maximum. 13 the responsibility lies with the user to ensure that the device is operated in such a manner that the maximum allowable junctio n temperature is not exceeded.
adsp-21990 ?20? rev. 0 peripherals electrical characteristics?ADSP-21990BBC parameter min typ max unit analog-to-digital converter ac specifications snr signal-to-noise ratio 1 68 71 db snrd signal-to-noise and distortion 1 64 68 db thd total harmonic distortion 1 ?72 ?66 db ctlk channel-channel crosstalk 1 ?78 ?66 db cmrr common-mode rejection ratio 1 ?74 ?66 db psrr power supply rejection ratio 1 0.05 0.2 %fsr accuracy inl integral nonlinearity 1 1.0 2.0 lsb dnl differential nonlinearity 1 0.5 1.25 lsb no missing codes 12 bits zero error 1 1.25 2.5 %fsr gain error 1 0.5 1.5 %fsr input voltage v in input voltage span 2.0 v c in input capacitance 2 10 pf conversion time fclk adc clock rate 18.75 mhz t conv total conversion time all 8 channels 773 ns voltage reference internal voltage reference 3 0.94 0.98 1.02 v output voltage tolerance 40 mv output current 100 a load regulation 4 0.5 2 mv power supply rejection ratio 0.5 2 mv reference input resistance 8 k ? power-on reset v rst reset threshold voltage 1.4 2.1 v v hyst hysteresis voltage 50 mv 1 in all cases, the input frequency to the adc system is assumed to be <100 khz. 2 analog input pins vin0 to vin7. 3 these specifications are for operation of the internal voltage re ference so that sense = refcom, with the default 1.0 v operati ng mode. 4 operation with full 0.1 ma load current. for optimal operation, it is recommended to buffer the vref output voltage before usin g it in other parts of the system.
?21? rev. 0 adsp-21990 peripherals electrical characteristics?adsp-21990bst parameter min typ max unit analog-to-digital converter snr signal-to-noise ratio 1 68 72 db snrd signal-to-noise and distortion 1 68 71 db thd total harmonic distortion 1 ?80 ?68 db ctlk channel-channel crosstalk 1 ?78 ?66 db cmrr common-mode rejection ratio 1 ?74 ?66 db psrr power supply rejection ratio 1 0.05 0.2 %fsr accuracy inl integral nonlinearity 1 0.6 2.0 lsb dnl differential nonlinearity 1 0.5 1.25 lsb no missing codes 12 bits zero error 1 1.25 2.5 %fsr gain error 1 0.5 1.5 %fsr input voltage v in input voltage span 2.0 v c in input capacitance 2 10 pf conversion time fclk adc clock rate 20 mhz t conv total conversion time all 8 channels 725 ns voltage reference internal voltage reference 3 0.94 0.98 1.02 v output voltage tolerance 40 mv output current 100 a load regulation 4 ?2 +0.5 +2 mv power supply rejection ratio ?2 +0.5 +2 mv reference input resistance 8 k ? power-on reset v rst reset threshold voltage 1.4 2.1 v v hyst hysteresis voltage 50 mv 1 in all cases, the input frequency to the adc system is assumed to be <100 khz. 2 analog input pins vin0 to vin7. 3 these specifications are for operation of the internal voltage re ference so that sense = refcom, with the default 1.0 v operati ng mode. 4 operation with full 0.1 ma load current. for optimal operation, it is recommended to buffer the vref output voltage before usin g it in other parts of the system.
adsp-21990 ?22? rev. 0 absolute maximum ratings esd sensitivity timing specifications this section contains timing information for the dsp external signals. use the exact information given. do not attempt to derive parameters from the addition or subtraction of other information. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, parameters cannot be added meaningfully to derive longer times. switching characteristics specify how the processor changes its signals. no control is possible over this timing; circuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics indicate what the processor will do in a given circumstance. switching character- istics can also be used to ensure that any timing requirement of a device connected to the processo r (such as memory) is satisfied. timing requirements apply to signals that are controlled by circuitry external to the processo r, such as the data input for a read operation.timing requirements guarantee that the processor operates correctly with other devices. internal (core) supply voltage(v ddint ) 1 . . ?0.3 v to +3.0 v 1 stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. external (i/o) supply voltage (v ddext ) 1 . . . ?0.3 v to +4.6 v input voltage (v il ?v ih ) 1, 2 . . . . . . . . . . . . . ?0.5 v to +5.5 v 2 except clkin and analog pins. output voltage swing (v ol ?v oh ) 1, 2 . . . . . . ?0.5 v to +5.5 v load capacitance (c l ) 1 . . . . . . . . . . . . . . . . . . . . . . 200 pf core clock period (t cclk ) 1 . . . . . . . . . . . . . . . . . . . . 6.25 ns core clock frequency (f cclk ) 1 . . . . . . . . . . . . . . 160 mhz peripheral clock period (t hclk ) 1 . . . . . . . . . . . . . . . 12.5 ns peripheral clock frequency (f hclk ) 1 . . . . . . . . . . . 80 mhz storage temperature range (t store ) 1 . . . .?65oc to +150oc lead temperature (5 seconds) (t lead ) 1 . . . . . . . . . . . 185oc caution esd (electrostatic discharge) sensitive devi ce. electrostatic charges as high as 4000 v readily accumulate on the hu man body and test equipment and can discharge without detection. although the ad sp-21990 features proprietary esd protection circuitry, permanent damage may occur on devices su bjected to high energy electrostatic discharges. therefore, proper esd precautio ns are recommended to avoid performance degradation or loss of functionality.
?23? rev. 0 adsp-21990 clock in and clock out cycle timing table 5 and figure 6 describe clock and reset operations. com- binations of clkin and clock multipliers must not select core/peripheral clocks in excess of 160 mhz/80 mhz for the adsp-21990bst and 150 mhz/75 mhz for the adsp- 21990bbc, when the peripheral clock rate is one-half the core clock rate. if the peripheral clock rate is equal to the core clock rate, the maximum peripheral clock rate is 80 mhz for the adsp-21990bst and 75 mhz for the ADSP-21990BBC. the peripheral clock is supplied to the clkout pins. when changing from bypass mode to pll mode, allow 512 hclk cycles for the pll to stabilize. table 5. clock in and clock out cycle timing parameter min max unit timing requirements t ck clkin period 1, 2 10 200 ns t ckl clkin low pulse 4.5 ns t ckh clkin high pulse 4.5 ns t wrst reset asserted pulsewidth low 200t clkout ns t mss mselx/bypass stable before reset deasserted setup 40 s t msh mselx/bypass stable after reset deasserted hold 1000 ns t msd mselx/bypass stable after reset asserted 200 ns t pfd flag output disable time after reset asserted 10 ns switching characteristics t ckod clkout delay from clkin 0 5.8 ns t cko clkout period 3 12.5 ns 1 in clock multiplier mode and msel6?0 set for 1:1 (or clkin = cclk), t ck = t cclk . 2 in bypass mode, t ck = t cclk . 3 clkout jitter can be as great as 8 ns wh en clkout frequency is less than 20 mhz. for fr equencies greater than 20 mhz, jitter is less than 1 ns. figure 6. clock in and clock out cycle timing t ckod clkout msel6?0 bypass df reset clkin t wrst t ckh t ck t ckl t msh t cko t pfd t msd t mss
adsp-21990 ?24? rev. 0 programmable flags cycle timing table 6 and figure 7 describe programmable flag operations. timer pwm_out cycle timing table 7 and figure 8 describe timer expired operations. the input signal is asynchronous in ?width capture mode? and has an absolute maximum input frequency of 40 mhz. table 6. programmable flags cycle timing parameter min max unit timing requirement t hfi flag input hold is asynchronous 3 ns switching characteristics t dfo flag output delay with respect to clkout 7 ns t hfo flag output hold after clkout high 6 ns figure 7. programmable flags cycle timing t dfo pf (input) t hfi pf (output) clkout flag input flag output t hfo table 7. timer pwm_out cycle timing parameter min max unit switching characteristic t hto timer pulsewidth output 1 12.5 (2 32 ?1) cycles ns 1 the minimum time for t hto is one cycle, and the maximum time for t hto equals (2 32 ?1) cycles. figure 8. timer pwm_out cycle timing hclk pwm_out t hto
?25? rev. 0 adsp-21990 external port write cycle timing table 8 and figure 9 describe external port write operations. the external port lets systems exte nd read/write accesses in three ways: wait states, ack input, and combined wait states and ack. to add waits with ack, the dsp must see ack low at the rising edge of emi clock. ack low causes the dsp to wait, and the dsp requires two emi cloc k cycles after ack goes high to finish the access. for more information, see the external port chapter in the adsp-2199x mixed signal dsp controller hardware reference . table 8. external port write cycle timing parameter 1, 2 min max unit timing requirements t akw ack strobe pulsewidth 12.5 ns t dwsak ack delay from xms low 0.5t emiclk ?1 ns switching characteristics t csws chip select asserted to wr asserted delay 0.5t emiclk ?4 ns t aw s address valid to wr setup and delay 0.5t emiclk ?3 ns t wscs wr deasserted to chip select deasserted 0.5t emiclk ?4 ns t wsa wr deasserted to address invalid 0.5t emiclk ?3 ns t ww wr strobe pulsewidth t emiclk ?2+w 3 ns t cda wr to data enable access delay 0 ns t cdd wr to data disable access delay 0.5t emiclk ?3 0.5t emiclk +4 ns t dsw data valid to wr deasserted setup t emiclk +1+w 3 t emiclk +7+w 3 ns t dhw wr deasserted to data invalid hold time; e_whc 4, 5 3.4 ns t dhw wr deasserted to data invalid hold time; e_whc 4, 6 t emiclk +3.4 ns t wwr wr deasserted to wr , rd asserted t hclk ns 1 t emiclk is the external memory interface clock period. t hclk is the peripheral clock period. 2 these are timing parameters that are based on worst-case operating conditions. 3 w = (number of wait states specified in wait register) t emiclk . 4 write hold cycle?memory select control registers (ms ctl). 5 write wait state count (e_wwc) = 0 6 write wait state count (e_wwc) = 1 figure 9. external port write cycle timing d15?0 t aws t ww t akw t dhw t cdd ack wr a21?0 ms3C0 ioms bms t csws t wsa t wscs t cda rd t dsw t wwr t dwsak
adsp-21990 ?26? rev. 0 external port read cycle timing table 9 and figure 10 describe external port read operations. for additional information on the ack signal, see the discussion on page 25 . table 9. external port read cycle timing parameter 1, 2 min max unit timing requirements t akw ack strobe pulsewidth t hclk ns t rda rd asserted to data access setup t emiclk ?5+w 3 ns t ada address valid to data access setup t emiclk +w 3 ns t sda chip select asserted to data access setup t emiclk +w 3 ns t sd data valid to rd deasserted setup 5 ns t hrd rd deasserted to data invalid hold 0 ns t drsak ack delay from xms low 0.5t emiclk ?1 ns switching characteristics t csrs chip select asserted to rd asserted delay 0.5t emiclk ?3 ns t ars address valid to rd setup and delay 0.5t emiclk ?3 ns t rscs rd deasserted to chip sel ect deasserted setup 0.5t emiclk ?2 ns t rw rd strobe pulsewidth t emiclk ?2+w 3 ns t rsa rd deasserted to addr ess invalid setup 0.5t hclk ?2 ns t rwr rd deasserted to wr , rd asserted t hclk 1 t emiclk is the external memory interface clock period. t hclk is the peripheral clock period. 2 these are timing parameters that are based on worst-case operating conditions. 3 w = (number of wait states specified in wait register) t emiclk . figure 10. external po rt read cycle timing t ars d15?0 t rw t akw t cda t rda t ada t sda t sd t hrd ack rd a21?0 t csrs t rsa t rscs t rwr ms3?0 ioms bms wr t drsak
?27? rev. 0 adsp-21990 external port bus request/grant cycle timing table 10 and figure 11 describe external port bus request and bus grant operations. table 10. external port bus request and grant cycle timing parameter 1, 2 min max unit timing requirements t bs br asserted to clkout high setup 4.6 ns t bh clkout high to br deasserted hold time 0 ns switching characteristics t sd clkout high to xms , address, and rd / wr disable 0.5t hclk +1 ns t se clkout low to xms , address, and rd / wr enable04ns t dbg clkout high to bg asserted setup 04ns t ebg clkout high to bg deasserted hold time 0 4 ns t dbh clkout high to bgh asserted setup 0 4 ns t ebh clkout high to bgh deasserted hold time04ns 1 t hclk is the peripheral clock period. 2 these are timing parameters that are based on worst-case operating conditions. figure 11. external port bus request and grant cycle timing t bh a21?0 clkout t bs t sd t sd t sd t dbg t dbh t se t se t se t ebg t ebh bgh wr rd ms3?0 ioms bms br bg
adsp-21990 ?28? rev. 0 serial port timing table 11 and figure 12 describe sport transmit and receive operations, while figure 13 and figure 14 describe sport frame sync operations. table 11. serial port 1, 2 parameter min max unit external clock timing requirements t sfse tfs/rfs setup before tclk/rclk 3 4ns t hfse tfs/rfs hold after tclk/rclk 3 4ns t sdre receive data setup before rclk 3 1.5 ns t hdre receive data hold after rclk 3 4ns t sclkw tclk/rclk width 0.5t hclk ?1 ns t sclk tclk/rclk period 2t hclk ns internal clock timing requirements t sfsi tfs setup before tclk 4 ; rfs setup before rclk 3 4ns t hfsi tfs/rfs hold after tclk/rclk 3 3ns t sdri receive data setup before rclk 3 2ns t hdri receive data hold after rclk 3 5ns external or internal clock switching characteristics t dfse tfs/rfs delay after tclk/rclk (internally generated fs) 4 14 ns t hofse tfs/rfs hold after tclk/rclk (internally generated fs) 4 3ns external clock switching characteristics t ddte transmit data delay after tclk 4 13.4 ns t hdte transmit data hold after tclk 4 4ns internal clock switching characteristics t ddti transmit data delay after tclk 4 13.4 ns t hdti transmit data hold after tclk 4 4ns t sclkiw tclk/rclk width 0.5t hclk ?3.5 0.5t hclk +2.5 ns enable and three-state 5 switching characteristics t dtene data enable from external tclk 4 012.1ns t ddtte data disable from external tclk 4 13 ns t dteni data enable from internal tclk 4 013ns t ddtti data disable from external tclk 4 12 ns external late frame sync switching characteristics t ddtlfse data delay from late external tfs with mce=1, mfd=0 6, 7 10.5 ns t dtenlfse data enable from late fs or mce=1, mfd=0 6, 7 3.5 ns 1 to determine whether communication is possible between two devices at clock speed n, the following specifications must be confi rmed: 1) frame sync delay and frame sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) sclk width. 2 word selected timing for i 2 s mode is the same as tfs/rfs timing (normal framing only). 3 referenced to sample edge. 4 referenced to drive edge. 5 only applies to sport. 6 mce=1, tfs enable, and tfs valid follow t ddtenfs and t ddtlfse . 7 if external rfsd/tfs s etup to rclk/tclk>0.5t lsck , t ddtlsck and t dtenlsck apply; otherwise, t ddtlfse and t dtenlfs apply.
?29? rev. 0 adsp-21990 figure 12. serial port dt dt t ddtte t ddten t ddtti t ddtin drive edge drive edge drive edge drive edge tclk/rclk tclk/rclk tclk (ext) tfs (?late,? ext.) t sdri rclk rfs dr drive edge sample edge t hdri t sfsi t hfsi t dfse t hofse t sclkiw data receive-internal clock t sdre data receive-external clock rclk rfs dr drive edge sample edge t hdre t sfse t hfse t dfse t sclkw t hofse note: either the rising edge or falling edge of rclk or tclk can be used as the active sampling edge. t ddti t hdti tclk tfs dt drive edge sample edge t sfsi t hfsi t sclkiw t dfse t hofse data transmit-internal clock t ddte t hdte tclk tfs dt drive edge sample edge t sfse t hfse t dfse t sclkw t hofse data transmit-external clock note: either the rising edge or falling edge of rclk or tclk can be used as the active sampling edge. tclk (int) tfs (?late,? int.)
adsp-21990 ?30? rev. 0 figure 13. serial port?e xternal late frame sync (frame sync setup > 0.5t sclk ) figure 14. serial port?e xternal late frame sync (frame sync setup < 0.5t hclk ) drive sample drive t dtenlfse t ddtlfse external rfs with mce = 1, mfd = 0 1st bit 2nd bit dt rclk rfs late external tfs t hdte/ i t ddte/ i t sfse /i drive sample drive t dtenlfse t ddtlfse 1st bit 2nd bit dt tclk tfs t hdte/ i t ddte/i t hosfse/ i t hosfse/ i t sfse/i t ddtlfse drive sample drive t dtenlfse t ddtlfse external rfs with mce = 1, mfd = 0 1st bit 2nd bit dt rclk rfs late external tfs t hdte/ i t ddte/i t sfse/ i drive sample drive t dtenlfse 1st bit 2nd bit dt tclk tfs t hdte/ i t ddte/ i t hofse/i t hofse/ i t sfse/i
?31? rev. 0 adsp-21990 serial peripheral interface port?master timing table 12 and figure 15 describe spi port master operations. table 12. serial peripheral interface (spi) port?master timing parameter min max unit timing requirements t sspid data input valid to sclk edge (data input setup) 8 ns t hspid sclk sampling edge to data input invalid (data in hold) 1 ns switching characteristics t sdscim spisel low to first sclk edge 2t hclk ?3 ns t spichm serial clock high period 2t hclk ?3 ns t spiclm serial clock low period 2t hclk ?3 ns t spiclk serial clock period 4t hclk ?1 ns t hdsm last sclk edge to spisel high 2t hclk ?3 ns t spitdm sequential transfer delay 2t hclk ?2 ns t ddspid sclk edge to data output valid (data out delay) 0 6 ns t hdspid sclk edge to data output invalid (data out hold) 0 5 ns figure 15. serial peripheral interface (spi) port?master timing t hspid t hdspid lsb msb t hspid t ddspid mosi (output) miso (input) spisel (output) sclk (cpol = 0) (output) sclk (cpol = 1) (output) t spichm t spiclm t spiclm t spiclk t spichm t hdsm t spitdm t hdspid lsb valid lsb msb msb valid t hspid t ddspid mosi (output) miso (input) t sspid t sdscim t sspid cpha = 1 cpha = 0 msb valid lsb valid t sspid
adsp-21990 ?32? rev. 0 serial peripheral interface port?slave timing table 13 and figure 16 describe spi port slave operations. table 13. serial peripheral interface (spi) port?slave timing parameter min max unit timing requirements t spichs serial clock high period 2t hclk ns t spicls serial clock low period 2t hclk ns t spiclk serial clock period 4t hclk ns t hds last spiclk edge to spiss not asserted 2t hclk ns t spitds sequential transfer delay 2t hclk +4 ns t sdsci spiss assertion to first spiclk edge 2t hclk ns t sspid data input valid to sclk edge (data input setup) 1.6 ns t hspid sclk sampling edge to data input invalid (data in hold) 2.4 ns switching characteristics t dsoe spiss assertion to data out active 0 8 ns t dsdhi spiss deassertion to data high impedance 0 10 ns t ddspid sclk edge to data out valid (data out delay) 0 10 ns t hdspid sclk edge to data out invalid (data out hold) 0 10 ns figure 16. serial peripheral interface (spi) port?slave timing t hspid t ddspid t dsdhi lsb msb msb valid t hspid t dsoe t hdspid miso (output) mosi (input) spiss (input) sclk (cpol = 0) (input) sclk (cpol = 1) (input) t spichs t spicls t spicls t spiclk t hds t spichs t sspid t hspid t dsdhi lsb valid msb msb valid t dsoe t ddspid miso (output) mosi (input) lsb valid lsb t spitds t ddspid cpha = 0 cpha = 1 t sdsci t sspid t sspid
?33? rev. 0 adsp-21990 jtag test and emulation port timing table 14 and figure 17 describe jtag port operations. table 14. jtag port timing parameter min max unit timing requirements t tck tck period 20 ns t stap tdi, tms setup before tck high 4 ns t htap tdi, tms hold after tck high 4 ns t ssys system inputs setu p before tck low 1 4ns t hsys system inputs hold after tck low 1 5ns t trstw trst pulsewidth 2 4t tck ns switching characteristics t dtdo tdo delay from tck low 8 ns t dsys system outputs delay after tck low 3 022ns 1 system inputs = data15?0, addr21?0, rd, wr, ack, br, bg, pf15?0, dr, tclk, rclk , tfs, rfs, clkin, reset. 2 50 mhz maximum. 3 system outputs = data15?0, addr21?0, ms3?0, rd, wr , ack, clkout, bg , pf15?0, dt, tclk 0, tclk, rclk, tfs, rfs, bms. figure 17. jtag port timing tms tdi tdo system inputs system outputs tck t tck t htap t stap t dtdo t ssys t hsys t dsys
adsp-21990 ?34? rev. 0 power dissipation total power dissipation has two co mponents, one due to internal circuitry and one due to the switching of external output drivers. internal power dissipation is dependent on the instruction execution sequence and the data operands involved. the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: ? number of output pins that switch during each cycle (o) ? the maximum frequency at wh ich they can switch (f) ? their load ca pacitance (c) ? their voltage swing (v dd ) and is calculated by the formula below. the load capacitance includes th e processor package capacitance (c in ). the switching frequency incl udes driving the load high and then back low. address and da ta pins can drive high and low at a maximum rate of 1/(2t ck ). the write strobe can switch every cycle at a frequency of 1/t ck . select pins switch at 1/(2t ck ), but selects can switch on each cycle. for example, estimate p ext with the following assumptions: ? a system with one bank of external data memory?asyn- chronous ram (16-bit) ? one 64k 16 ram chip is used with a load of 10 pf ? maximum peripheral speed cclk = 80 mhz, hclk = 80 mhz ? external data memory writes occur every other cycle, a rate of 1/(4t hclk ), with 50% of the pins switching ? the bus cycle time is 80 mhz (t hclk = 12.5 ns) the p ext equation is calculated for each class of pins that can drive as shown in table 15 . a typical power consumption can now be calculated for these conditions by adding a typical in ternal power dissipation with the following formula. where: ? p ext is from table 15 . ? p int is i ddint 2.5 v, using the calculation i ddint listed in power dissipation . note that the conditions causing a worst-case p ext are different from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pins are switching from all ones to all zeros. note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. test conditions the dsp is tested for output en able, disable, and hold time. output disable time output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by ? v is dependent on the capacitive load, c l and the load current, i l . this decay time can be approximated by the following equation. the output disable time t dis is the difference between t measured and t decay as shown in figure 18 . the time t measured is the interval from when the referenc e signal switches to when the output voltage decays ? v from the measured output high or output low voltage. the t decay i s c a l c u l a t e d w i t h t e s t l o a d s c l and i l , and with ? v equal to 0.5 v. p ext oc v dd 2 f = table 15. p ext calculation example pin type number of pins % switching c f v dd 2 = p ext address 15 50 10 pf 20 mhz 10.9 v = 0.01635 w msx 1 0 10 pf 20 mhz 10.9 v = 0.0 w wr 1 10 pf 40 mhz 10.9 v = 0.00436 w data 16 50 10 pf 20 mhz 10.9 v = 0.01744 w clkout 1 10 pf 80 mhz 10.9 v = 0.00872 w =0.04687 w p total p = ext p int + figure 18. output enable/disable t decay c l v ? i l --------------- = reference signal t dis output starts driving v oh (measured) ? v2.0v v ol (measured) + v1.0v t measured v oh (measured) v ol (measured) high impedance state. test conditions cause this voltage to be approximately 1.5v output stops driving t decay t ena
?35? rev. 0 adsp-21990 output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. the output enable time t ena is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram ( figure 18 ). if multiple pins (such as the data bus) ar e enabled, the measurement value is that of the first pin to start driving. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation at output disable time on page 34 . choose ? v to be the difference between the adsp- 21990 output voltage and the in put threshold for the device requiring the hold time. a typical ? v will be 0.4 v. c l is the total bus capacitance (per data line), and i l is the total leakage or three- state current (per data line). the hold time will be t decay plus the minimum disable time (i.e., t datrwh for the write cycle). pin configurations table 16 identifies the signal for each mini-bga ball number. table 17 identifies the mini-bga ball number for each signal name. table 18 identifies the signal for each lqfp lead. table 19 identifies the lqfp lead for each signal name. table 4 describes each pin name. figure 19. equivalent device loading for ac measurements (inclu des all fixtures) figure 20. voltage reference levels for ac measurements (except ou tput enable/disable) 1.5v 50pf to output pin i ol i oh input or output 1.5v 1.5v
adsp-21990 ?36? rev. 0 table 16. 196-ball mini-bga ball number by signal pin name ball no. pin name ball no. pin name ball no. pin name ball no. a0 n1 convst g13 nc e6 pf15 d14 a1 n2 d0 p10 nc e7 por h13 a2 m1 d1 n9 nc e8 pwmpol m11 a3 m2 d2 p9 nc e9 pwmsync n13 a4 l1 d3 n8 nc e10 pwmsr n14 a5 l2 d4 p8 nc f5 pwmtrip m12 a6 k1 d5 n7 nc f6 rclk b2 a7 k2 d6 p7 nc f7 rd c2 a8 j1 d7 n6 nc f8 reset h14 a9 j2 d8 p6 nc f9 rfs a4 a10 h1 d9 n5 nc f10 sck b1 a11 h2 d10 p5 nc g5 sense b8 a12 g1 d11 n4 nc g6 tck j13 a13 g2 d12 p4 nc g7 tclk b3 a14 f1 d13 n3 nc g8 tdi j14 a15 f2 d14 p3 nc g9 tdo k14 a16 e1 d15 p2 nc g10 tfs b4 a17 e2 dr a2 nc h5 tmr0 h12 a18 d1 dt a3 nc h6 tmr1 g12 a19 d2 eia e12 nc h7 tmr2 f13 ack d4 eib e13 nc h8 tms j12 ah n11 eis e14 nc h9 trst k13 al m10 eiz f12 nc h10 vddext d11 ashan b6 emu k12 nc j5 vddext e5 auxtrip d10 gnd e4 nc j6 vddext h11 aux1 d12 gnd e11 nc j7 vddext j4 aux0 d13 gnd f4 nc j8 vddext l4 avdd d5 gnd g11 nc j9 vddext l6 avdd d6 gnd h4 nc j10 vddext l9 av s s d 7 g n d j 1 1 n c m 8 vd d e x t l 1 0 av s s d 8 g n d k 4 n c n 1 2 vd d e x t m 5 bg f3 gnd k5 nc p1 vddext m7 bgh g3 gnd k6 nc p13 vddint g4 bl p11 gnd k7 nc p14 vddint l5 bh p12 gnd k8 pf0/ spiss a10 vddint l7 bmode0 m14 gnd k9 pf1/spisel1 b10 vddint l8 bmode1 l13 gnd k10 pf2/spisel2 c10 vddint k11 bmode2 l12 gnd l11 pf3/spisel3 d9 vddint f11 bms j3 gnd m4 pf4/spisel4 a11 vin0 a7 br c1 gnd m6 pf5/spisel5 b11 vin1 a8 bshan a6 ioms d3 pf6/spisel6 a12 vin2 b7 bypass m13 miso c3 pf7/spisel7 a13 vin3 a9 capb b9 mosi c4 pf8 b12 vin4 a5 capt c7 ms0 k3 pf9 b13 vin5 c6 ch n10 ms1 l3 pf10 c11 vin6 b5 cl m9 ms2 m3 pf11 c12 vin7 c5 clkin l14 ms3 h3 pf12 c13 vref c8 clkout g14 nc a1 pf13 b14 wr e3 cml c9 nc a14 pf14 c14 xtal f14
?37? rev. 0 adsp-21990 table 17. 196-ball mini-bga signal by ball number ball no. pin name ball no. pin name ball no. pin name ball no. pin name a1 nc d8 avss h1 a10 l8 vddint a2 dr d9 pf3/spisel3 h2 a11 l9 vddext a3 dt d10 auxtrip h3 ms3 l10 vddext a4 rfs d11 vddext h4 gnd l11 gnd a5 vin4 d12 aux1 h5 nc l12 bmode2 a6 bshan d13 aux0 h6 nc l13 bmode1 a7 vin0 d14 pf15 h7 nc l14 clkin a8 vin1 e1 a16 h8 nc m1 a2 a9 vin3 e2 a17 h9 nc m2 a3 a10 pf0/ spiss e3 wr h10 nc m3 ms2 a11 pf4/spisel4 e4 gnd h11 vddext m4 gnd a12 pf6/spisel6 e5 vddext h12 tmr0 m5 vddext a13 pf7/spisel7 e6 nc h13 por m6 gnd a14 nc e7 nc h14 reset m7 vddext b1 sck e8 nc j1 a8 m8 nc b2 rclk e9 nc j2 a9 m9 cl b3 tclk e10 nc j3 bms m10 al b4 tfs e11 gnd j4 vddext m11 pwmpol b5 vin6 e12 eia j5 nc m12 pwmtrip b6 ashan e13 eib j6 nc m13 bypass b7 vin2 e14 eis j7 nc m14 bmode0 b8 sense f1 a14 j8 nc n1 a0 b9 capb f2 a15 j9 nc n2 a1 b10 pf1/spisel1 f3 bg j10 nc n3 d13 b11 pf5/spisel5 f4 gnd j11 gnd n4 d11 b12 pf8 f5 nc j12 tms n5 d9 b13 pf9 f6 nc j13 tck n6 d7 b14 pf13 f7 nc j14 tdi n7 d5 c1 br f8 nc k1 a6 n8 d3 c2 rd f9 nc k2 a7 n9 d1 c3 miso f10 nc k3 ms0 n10 ch c4 mosi f11 vddint k4 gnd n11 ah c5 vin7 f12 eiz k5 gnd n12 nc c6 vin5 f13 tmr2 k6 gnd n13 pwmsync c7 capt f14 xtal k7 gnd n14 pwmsr c8 vref g1 a12 k8 gnd p1 nc c9 cml g2 a13 k9 gnd p2 d15 c10 pf2/spisel2 g3 bgh k10 gnd p3 d14 c11 pf10 g4 vddint k11 vddint p4 d12 c12 pf11 g5 nc k12 emu p5 d10 c13 pf12 g6 nc k13 trst p6 d8 c14 pf14 g7 nc k14 tdo p7 d6 d1 a18 g8 nc l1 a4 p8 d4 d2 a19 g9 nc l2 a5 p9 d2 d3 ioms g10 nc l3 ms1 p10 d0 d4 ack g11 gnd l4 vddext p11 bl d5 avdd g12 tmr1 l5 vddint p12 bh d6 avdd g13 convst l6 vddext p13 nc d7 avss g14 clkout l7 vddint p14 nc
adsp-21990 ?38? rev. 0 table 18. 176-lead lqfp signal by lead number lead no. signal lead no. signal lead no. signal lead no. signal 1nc45vddext89nc133vddext 2nc46a490nc134pf11 3 vddext 47 a3 91 vddext 135 pf10 4rclk48a292bypass136pf9 5 sck 49 a1 93 bmode0 137 pf8 6miso50a094bmode1138pf7/spisel7 7 mosi 51 d15 95 bmode2 139 pf6/spisel6 8 rd 52 d14 96 nc 140 pf5/spisel5 9 wr 53 d13 97 gnd 141 pf4/spisel4 10 ack 54 d12 98 vddint 142 gnd 11 br 55 d11 99 emu 143 vddext 12 bg 56 gnd 100 trst 144 pf3/spisel3 13 bgh 57 vddext 101 tdo 145 pf2/spisel2 14 ioms 58 gnd 102 tdi 146 pf1/spisel1 15 bms 59 vddint 103 tms 147 pf0/ spiss 16 ms3 60 d10 104 tck 148 gnd 17 gnd 61 d9 105 por 149 vddint 18 vddext 62 d8 106 reset 150 avss 19 ms2 63 d7 107 clkin 151 avdd 20 ms1 64 d6 108 xtal 152 nc 21 ms0 65 d5 109 clkout 153 vref 22 gnd 66 gnd 110 convst 154 cml 23 vddint 67 vddint 111 tmr0 155 capt 24 a19 68 d4 112 gnd 156 capb 25 a18 69 d3 113 vddext 157 sense 26 a17 70 d2 114 tmr1 158 vin3 27 a16 71 d1 115 tmr2 159 vin2 28 a15 72 d0 116 eis 160 vin1 29 a14 73 nc 117 gnd 161 vin0 30 a13 74 gnd 118 vddint 162 ashan 31 gnd 75 vddext 119 eiz 163 bshan 32 vddext 76 cl 120 eib 164 vin4 33 a12 77 ch 121 eia 165 vin5 34 a11 78 bl 122 auxtrip 166 vin6 35 a10 79 bh 123 aux1 167 vin7 36 a9 80 al 124 aux0 168 avss 37 a8 81 ah 125 pf15 169 avdd 38 a7 82 nc 126 pf14 170 dt 39 a6 83 nc 127 pf13 171 dr 40 a5 84 pwmsync 128 pf12 172 rfs 41 gnd 85 pwmpol 129 gnd 173 tfs 42 nc 86 pwmsr 130 nc 174 tclk 43 nc 87 pwmtrip 131 nc 175 gnd 44 nc 88 gnd 132 nc 176 nc
?39? rev. 0 adsp-21990 table 19. 176-lead lqfp lead number by signal signal lead no. signal lead no. signal lead no. signal lead no. a0 50 capb 156 eis 116 pwmtrip 87 a1 49 capt 155 eiz 119 rclk 4 a10 35 ch 77 emu 99 rd 8 a11 34 cl 76 ioms 14 reset 106 a12 33 clkin 107 miso 6 rfs 172 a13 30 clkout 109 mosi 7 sck 5 a14 29 cml 154 ms0 21 sense 157 a15 28 convst 110 ms1 20 tck 104 a16 27 d0 72 ms2 19 tclk 174 a17 26 d1 71 ms3 16 tdi 102 a18 25 d10 60 nc 1 tdo 101 a19 24 d11 55 nc 2 tfs 173 a2 48 d12 54 nc 42 tmr0 111 a3 47 d13 53 nc 43 tmr1 114 a4 46 d14 52 nc 44 tmr2 115 a5 40 d15 51 nc 83 tms 103 a6 39 d2 70 nc 89 trst 100 a7 38 d3 69 nc 90 vddext 3 a8 37 d4 68 nc 96 vddext 18 a9 36 d5 65 nc 130 vddext 32 ack 10 d6 64 nc 131 vddext 45 ah 81 d7 63 nc 132 vddext 57 al 80 d8 62 nc 152 vddext 75 ashan 162 d9 61 nc 176 vddext 91 aux0 124 gnd 17 pf0/ spiss 147 vddext 113 aux1 123 gnd 22 pf1/spisel1 146 vddext 133 auxtrip 122 gnd 31 pf10 135 vddext 143 avdd 151 gnd 41 pf11 134 vddint 23 avdd 169 gnd 56 pf12 128 vddint 59 avss 150 gnd 58 pf13 127 vddint 67 avss 168 gnd 66 pf14 126 vddint 98 bg 12 gnd 74 pf15 125 vddint 118 bgh 13 gnd 88 pf2/spisel2 145 vddint 149 bh 79 gnd 97 pf3/spisel3 144 vin0 161 bl 78 gnd 112 pf4/spisel4 141 vin1 160 bmode0 93 gnd 117 pf5/spisel5 140 vin2 159 bmode1 94 gnd 129 pf6/spisel6 139 vin3 158 bmode2 95 gnd 142 pf7/spisel7 138 vin4 164 bms 15 gnd 148 pf8 137 vin5 165 br 11 gnd 175 pf9 136 vin6 166 bshan 163 dr 171 por 105 vin7 167 bypass 92 dt 170 pwmpol 85 vref 153 nc 73 eia 121 pwmsr 86 wr 9 nc 82 eib 120 pwmsync 84 xtal 108
adsp-21990 ?40? rev. 0 outline dimensions dimensions shown in millimeters. 196-ball mini-bga (bc-196-2) 176-lead lqfp (st-176-1) detail b detail a seating plane detail a ball diameter 0.55 nom 0.20 max ball coplanarity 13.00 bsc a b c d e f g h j k l m n p 98 7 65 4321 detail b 1.00 bsc 15.00 bsc sq top view bottom view 1.00 bsc notes: 1. the actual position of the ball grid is within 0.25 of its ideal position relative to the package edges. 2. the actual position of each ball is within 0.10 of its ideal position relative to the ball grid. 3. dimensions comply with jedec standard mo-192 variation aae-1 with the exception of maximum height. 4. center dimensions are nominal. 1.85 1.70 1.55 13.00 bsc 10 11 12 13 14 0.70 0.60 0.50 0.57 0.52 0.47 0.75 0.70 0.65 1.10 1.00 0.90 1.10 1.00 0.90 top view (pins down) pin 1 133 1 132 45 44 88 89 176 26.00 bsc sq 24.00 bsc sq 0.27 0.22 typ 0.17 0.50 bsc lead pitch 0.75 0.60 0.45 seating plane 1.60 max 0.15 0.05 0.08 max lead coplanarity 1.45 1.40 1.35 detail a notes: 1. dimensions in millimeters. 2. actual position of each lead is within 0.08 of its ideal position, when measured in the lateral direction. 3. center dimensions are nominal. 4. dimensions comply with jedec standard ms-026-bga. detail a
?41? rev. 0 adsp-21990 ordering guide part number ambient temperature range ins truction rate operating voltage package ADSP-21990BBC ?40oc to +85oc 150 mhz 2.5 int./3.3 ext. v 196-ball mini-bga adsp-21990bst ?40oc to +85oc 160 mhz 2 .5 int./3.3 ext. v 176-lead lqfp
?42?
?43?
?44? c02893?0?5/03(0)

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